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AM79Q4457 Scheda tecnica(PDF) 9 Page - List of Unclassifed Manufacturers

Il numero della parte AM79Q4457
Spiegazioni elettronici  Quad Subscriber Line Audio Processing Circuit-Non-Programmable (QSLAC-NP) Devices
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Produttore elettronici  ETC1 [List of Unclassifed Manufacturers]
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SLAC Products
9
Power Supply for the Am79Q4457/5457
Devices:
AGND
Analog Ground
DGND
Digital Ground
V
CCA
+5.0 V Analog Power Supply
V
CCD
+5.0 V Digital Power Supply
Two separate power supply inputs are provided to allow
for noise isolation and good power supply decoupling
techniques; however, the two pins have a low imped-
ance connection inside the part. For best performance,
all of the +5.0 power supply pins should be connected to-
gether at the connector of the printed circuit board, and
all of the grounds should be connected together at the
connector of the printed circuit board.
MCLK
Input
Master Clock. The Master Clock frequency can be 1.536 MHz, 1.544 MHz, 2.048 MHz, or 4.096
MHz for use by the digital signal processor. Using the Transmit Frame Sync (FSX) Inputs, the
QSLAC-NP device determines the MCLK frequency and makes the necessary internal
adjustments automatically. The master clock frequency must be an exact integer multiple of the
frame sync frequency.
PCLK
Input
PCM Clock. The PCM clock determines the rate at which PCM data is serially shifted into or out
of the PCM ports. PCLK is an integer multiple of the frame sync frequency. The maximum clock
frequency is 4.096 MHz, and the minimum clock frequency is 256 kHz, due to a single PCM
highway. PCLK frequencies between 1.03 MHz and 1.53 MHz are not allowed. The digital signal
processor clock can be derived from PCLK by connecting MCLK and PCLK together. See frequency
restrictions under MCLK.
PDN
1, PDN2,
PDN
3, PDN4
Input
(Am79Q5457 Device Only) Power Down. The power-down inputs provide direct control over the
channel circuitry. A logic High on PDN
n (n = 1 to 4) powers Channel n down while a logic Low
powers the channel up. PDN
1 controls Channel 1, PDN2 controls Channel 2, PDN3 controls
Channel 3, and PDN
4 controls Channel 4. The PDN pins are used in the initialization of the internal
circuitry. Refer to the Power-Up Sequence section on 24 for initialization using the PDN pins.
TSCA
Output
Time Slot Control. The Time Slot Control output is an open drain output (requiring a pull-up resistor to
V
CCD) and is normally inactive (high impedance). TSCA is active (Low) when PCM data is transmitted
on the DXA pin for any of the four channels.
V
OUT1, VOUT2,
V
OUT3, VOUT4
Voltage
Analog Outputs. The received digital data at DRA is processed and converted to an analog signal
at the V
OUT pin. VOUT1 is the output from Channel 1; VOUT2 is the output for Channel 2; VOUT3 is the
output from Channel 3; and V
OUT4 is the output for Channel 4. The VOUT voltages are referenced
to V
REF1.
V
REF1
Output
Voltage Reference. The V
REF1 output is provided in order for an external 0.1-µF capacitor (or
larger) to be connected from V
REF1 to ground, filtering noise present on the internal voltage
reference. V
REF1 is buffered before it is used by internal circuitry. The voltage on VREF1 is nominally
2.1 V, and the output resistance is 115 kW. The leakage current in the capacitor must be less
than 20 nA. A larger filter capacitor will provide better filtering, but will increase the settling time.
V
REF2, VREF3
Input
(Am79Q4457 Device Only). Voltage Reference. V
REF2 and VREF3 are buffered and are available as
alternative reference voltages for the channel Digital-to-Analog (D-to-A) converters. The D-to-A
converters decode the received PCM data into analog voltage levels. V
REF1, VREF2, or VREF3 can be
selected by the Receive Gain Select (RGS) bits as the reference for the D-to-A converter in order to
select the receive gain of the channel.
Pin Name
Type
Description


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