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TMP47C201P Scheda tecnica(PDF) 9 Page - Toshiba Semiconductor |
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TMP47C201P Scheda tecnica(HTML) 9 Page - Toshiba Semiconductor |
9 / 32 page TOSHIBA CORPORATION 9/32 TMP47C101/201 Figure 2-8. Accessing Stack (Save/Restore) at the 47C201 (4) Count registers of the timer/counters (TC1, TC2) The 47C101/201 has two channels of 12-bit timer/ counters. The count register of the timer/counter is assigned with a RAM addresses in unit of 4 bits, so that the initial value is set and the contents are read by using the RAM manipulation instruction. The count registers are shared with the stack area (locations 13 and 14) described earlier, so that the stack is usable from location 13 when the timer/ counter 1 is not used. When none of timer/counter 1 and timer/counter 2 are used, the stack is usable from location 14. When both timer/counter 1 and timer/counter 2 are used, the data memory locations at addresses 77H and 7BH (37H and 3BH for the 47C101) can be used to store the user-processed data. Figure 2-9. Count Registers of the Timer/Counters (TC1, TC2) |
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