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SM89T16R1 Scheda tecnica(PDF) 11 Page - SyncMOS Technologies,Inc

Il numero della parte SM89T16R1
Spiegazioni elettronici  8-Bits Micro-controller With 64KB Flash ROM & IKB RAM & Two UART & RTC & ADC & PWM embedded
Download  34 Pages
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Produttore elettronici  SYNCMOS [SyncMOS Technologies,Inc]
Homepage  http://www.syncmos.com.tw
Logo SYNCMOS - SyncMOS Technologies,Inc

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SyncMOS Technologies Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & IKB RAM & Two UART & RTC & ADC & PWM embedded
Specifications subject to change without notice contact your sales representatives for the most recent information.
SM89T16R1 V1.0 JANUARY 2005
11
tAVDV2
9
Port2 Address valid to /WR or /RD LOW
1.5tCLCL–5
2.5 tCLCL–5
ns
tMCS =0
tMCS >0
tQVWX
9
Data valid to /WR transition
-5
1.0 tCLCL -5
ns
tMCS =0
tMCS >0
tWHQX
9
Data hold after /WR
1.0 tCLCL -5
2.0 tCLCL -5
ns
tMCS =0
tMCS >0
tRLAZ
8
/RD LOW to address float
0.5 tCLCL–5
ns
tWHLH
8,9
/RD or /WR HIGH to ALE HIGH
0
1.0 tCLCL -5
10
1.0 tCLCL +5
ns
tMCS =0
tMCS >0
Notes:
tMCS is time period related to the Stretch memory cycle selection. The following table shows the value of tMCS for each Stretch selection.
M2
M1
M0
MOVX Cycles
tMCS
0
0
0
2 machine cycles
0
0
0
1
3 machine cycles
4 tCLCL
0
1
0
4 machine cycles
8 tCLCL
0
1
1
5 machine cycles
12 tCLCL
1
0
0
6 machine cycles
16 tCLCL
1
0
1
7 machine cycles
20 tCLCL
1
1
0
8 machine cycles
24 tCLCL
1
1
1
9 machine cycles
28 tCLCL
Parameter
Figure
Symbol
Min
Typ
Max
Unit
Serial Port Clock Cycle Time
SM2=0,12 clocks per cycle
SM2=1,4 clocks per cycles
10
tXLXL
12 tCLCL
4 tCLCL
ns
ns
Output Data Setup to Clock Rising
SM2=0,12 clocks per cycle
SM2=1,4 clocks per cycles
10
tQVXH
12 tCLCL
4 tCLCL
ns
ns
Output Data Hold to Clock Rising
SM2=0,12 clocks per cycle
SM2=1,4 clocks per cycles
10
tXHQX
12 tCLCL
4 tCLCL
ns
ns
Input Data Hold to Clock Rising
SM2=0,12 clocks per cycle
SM2=1,4 clocks per cycles
10
tXHDX
12 tCLCL
4 tCLCL
ns
ns
Clock Rising Edge to Input Data Valid
SM2=0,12 clocks per cycle
SM2=1,4 clocks per cycles
10
tXHDV
12 tCLCL
4 tCLCL
ns
ns
Figure 4 External Clock Drive waveform
Figure 5 AC Testing Input/Output
Figure 6 AC Testing, Floating Waveform
Test Points
2.0V
0.8V
0.8V
2.0V
Notes:
AC inputs during testing are driven at 2.4V for logic “HIGH” and
0.45V for logic “LOW”. Timing measurements are at 2.0V for
logic “HIGH” and 0.8V for logic “LOW”
Floating
2.0V
0.8V
0.8V
2.0V
Notes:
The float state is define as the point which PORT 0 pins sinks
3.2mA or source 400
µA at the voltage test level.
tCHCX
tCLCX
0.8V
tCLCL
VIH1
tCLCH
tCHCL


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