GS8170LW36/72C-333/300/250/200

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 2.03 1/2005

11/27

© 2002, GSI Technology, Inc.

CMOS I/O SigmaRAMs are supplied with selectable (high or low) impedance output drivers. The ZQ pin allows selection between

SRAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive strength (ZQ high) point-to-point

applications.

Late Write, Pipelined Read Truth Table

CK

E1

E

ADV

W

B

Previous

Operation

Current Operation

DQ/CQ

DQ/CQ

0

→1

X

F

0

X

X

X

Bank Deselect

***/***

Hi-Z/Hi-Z

0

→1

X

X

1

X

X

Bank Deselect

Bank Deselect (Continue)

Hi-Z/Hi-Z

Hi-Z/Hi-Z

0

→1

1

T

0

X

X

X

Deselect

***/***

Hi-Z/CQ

0

→1

X

X

1

X

X

Deselect

Deselect (Continue)

Hi-Z/CQ

Hi-Z/CQ

0

→10

T

0

0

T

X

Write

Loads new address

Stores DQx if Bx = 0

***/***

D1/CQ

0

→10

T

0

0

F

X

Write (Abort)

Loads new address

No data stored

***/***

Hi-Z/CQ

0

→1X

X

1

X

T

Write

Write Continue

Increments address by 1

Stores DQx if Bx = 0

Dn-1/CQ

Dn/CQ

0

→1X

X

1

X

F

Write

Write Continue (Abort)

Increments address by 1

No data stored

Dn-1/CQ

Hi-Z/CQ

0

→10

T

0

1

X

X

Read

Loads new address

***/***

Q1/CQ

0

→1X

X

1

X

X

Read

Read Continue

Increments address by 1

Qn-1/CQ

Qn/CQ

Notes:

1. If E2 = EP2 and E3 = EP3, then E = “T” else E = “F”.

2. If one or more Bx = 0, then B = “T” else B = “F”.

3. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.

4. “***” indicates that the DQ input requirement / output state and CQ output state are determined by the previous operation.

5. DQs are tristated in response to Bank Deselect, Deselect, and Write commands, one full cycle after the command is sampled.

6. CQs are tristated in response to Bank Deselect commands only, one full cycle after the command is sampled.

7. Up to three (3) Continue operations may be initiated after a Read or Write operation is initiated to burst transfer up to four (4) distinct

pieces of data per single external address input. If a fourth (4th) Continue operation is initiated, the internal address wraps back to the ini-

tial external (base) address.