TDA9965 datasheet(2/22 Pages) PHILIPS

Il numero della parte	TDA9965

Spiegazioni elettronici	12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras

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Produttore elettronici	PHILIPS [NXP Semiconductors]

Homepage	http://www.nxp.com

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2004 Jul 05

2

Philips Semiconductors

Product speciﬁcation

12-bit, 5.0 V, 30 Msps analog-to-digital

interface for CCD cameras

TDA9965

FEATURES

• Clamp and Track/Hold (CTH) circuit with adjustable

bandwidth, Programmable Gain Amplifier (PGA), 12-bit

Analog-to-Digital Converter (ADC) and reference

regulator

• Fully programmable via a 3-wire serial interface

• Sampling frequency up to 30 MHz

• PGA gain from 0 to 36 dB (in 0.05 dB steps)

• CTH programmable bandwidth from 35 to 284 MHz

typical

• Standby mode (20 mW typical)

• Low power consumption of only 425 mW typical

• 5 V operation and 2.5 to 5.25 V operation for the digital

outputs

• TTL compatible inputs; TTL and CMOS compatible

outputs.

APPLICATIONS

• CCD camera systems.

GENERAL DESCRIPTION

The TDA9965 is a 12-bit analog-to-digital interface for a

CCD camera. The device includes a CTH circuit, PGA and

a low-power 12-bit ADC, together with its reference

voltage regulator.

The CTH has a bandwidth circuit controlled by on-chip

DACs via a serial interface.

A 10-bit digital clamp controls the ADC input clamp level.

ORDERING INFORMATION

QUICK REFERENCE DATA

Note

1. Noise and clamp behaviour are not guaranteed for a PGA gain higher than 30 dB.

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TDA9965HL

LQFP48

plastic low proﬁle quad ﬂat package; 48 leads; body 7

× 7 × 1.4 mm

SOT313-2

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

VCCA

analog supply voltage

4.75

5

5.25

V

VCCD

digital supply voltage

4.75

5

5.25

V

VCCO

digital output supply voltage

2.5

3

5.25

V

ICCA

analog supply current

with internal regulator

−

65

−

mA

ICCD

digital supply current

with internal regulator

−

19

−

mA

ICCO

digital output supply current

fpix = 30 MHz; CL =10pF on all

data outputs; ramp input

−

1

−

mA

ADCres

ADC resolution

−

12

−

bits

Vi(IN)(p-p)

CTH input voltage

(peak-to-peak value)

−

2

−

V

GCTH

CTH output ampliﬁer gain

−

0

−

dB

PGAdyn

PGA dynamic range

−

36

−

dB

fpix(max)

maximum pixel frequency

code fco(CTH) = 0000

30

−−

MHz

Ntot(rms)

total noise from CTH input to ADC

output (RMS value)

GPGA = 0 dB;

code fco(CTH) = 0000

−

0.85

−

LSB

Vn(i)(eq)(rms)

equivalent input noise

(RMS value)

GPGA = 30 dB;

code fco(CTH) = 0000; note 1

−

90

−µV

Ptot

total power consumption

−

425

−

mW

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