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TPS7A03 Scheda tecnica(PDF) 19 Page - Texas Instruments |
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TPS7A03 Scheda tecnica(HTML) 19 Page - Texas Instruments |
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19 / 43 page  R = DS(ON) V DO I RATED 19 TPS7A03 www.ti.com SBVS375B – JULY 2019 – REVISED APRIL 2020 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Excellent Transient Response The TPS7A03 includes several innovative circuits to ensure excellent transient response. Dynamic biasing increases the IQ for a short duration during transients to extend the closed-loop bandwidth and improve the output response time to transients. Adaptive biasing increases the IQ as the DC load current increases, extending the bandwidth of the loop. The response time across the output voltage range is constant because a buffered reference topology is used, which keeps the control loop in unity gain at any output voltage. These features give the device a wide loop bandwidth during transients that ensures excellent transient response while maintaining low IQ in steady-state conditions. 7.3.2 Active Discharge (P-Version Only) The device has an internal pulldown MOSFET that connects a RPULLDOWN resistor to ground when the device is disabled to actively discharge the output voltage. The active discharge circuit is activated by the enable pin or by the undervoltage lockout (UVLO). Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input supply has collapsed because reverse current can possibly flow from the output to the input. This reverse current flow can cause damage to the device. Limit reverse current to no more than 5% of the device rated current for a short period of time. 7.3.3 Low IQ in Dropout In most LDOs the IQ significantly increases when the device is placed into dropout, which is especially true for low IQ LDOs. The TPS7A03 helps to reduce the battery discharge by detecting when the device is operating in dropout conditions and maintaining a low IQ. 7.3.4 Smart Enable The enable pin for the device is an active-high pin. The output voltage is enabled when the voltage of the enable pin is greater than the high-level input voltage of the EN pin and disabled with the enable pin voltage is less than the low-level input voltage of the EN pin. If independent control of the output voltage is not needed, connect the enable pin to the input of the device. This device has a smart enable circuit to reduce quiescent current. When the voltage on the enable pin is driven above VEN(HI), as listed in the Electrical Characteristics table, the device is enabled and the smart enable internal pulldown resistor (REN(PULLDOWN)) is disconnected. When the enable pin is floating, the REN(PULLDOWN) is connected and pulls the enable pin low to disable the device. The REN(PULLDOWN) value is listed in the Electrical Characteristics table. This device has an internal pulldown circuit that activates when the device is disabled to actively discharge the output voltage. 7.3.5 Dropout Voltage Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the nominal output regulation, then the output voltage falls as well. For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for that current scales accordingly. Use Equation 1 to calculate the RDS(ON) of the device. (1) |
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Descrizione simile - TPS7A03_V06 |
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