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TPS7A03 Scheda tecnica(PDF) 28 Page - Texas Instruments |
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TPS7A03 Scheda tecnica(HTML) 28 Page - Texas Instruments |
28 / 43 page C IN C OUT OUT IN GND EN A2 B2 A1 B1 Via COUT VOUT VIN GND PLANE CIN Represents via used for application specific connections 1 2 3 4 5 COUT VOUT VIN GND PLANE CIN Represents via used for application specific connections 1 2 3 4 28 TPS7A03 SBVS375B – JULY 2019 – REVISED APRIL 2020 www.ti.com Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated 10 Layout 10.1 Layout Guidelines • Place input and output capacitors as close to the device as possible. • Use copper planes for device connections to optimize thermal performance. • Place thermal vias around the device to distribute the heat. • Do not place a thermal via directly beneath the thermal pad of the DQN package. A via can wick solder or solder paste away from the thermal pad joint during the soldering process, leading to a compromised solder joint on the thermal pad. 10.2 Layout Examples Figure 64. Layout Example for the DQN Package Figure 65. Layout Example for the DBV Package Figure 66. Layout Example for the YCH Package |
Codice articolo simile - TPS7A03_V06 |
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Descrizione simile - TPS7A03_V06 |
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