Motore di ricerca datesheet componenti elettronici |
|
IMX8MNCEC Scheda tecnica(PDF) 51 Page - NXP Semiconductors |
|
IMX8MNCEC Scheda tecnica(HTML) 51 Page - NXP Semiconductors |
51 / 89 page Electrical characteristics i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 0.1, 03/2020 NXP Semiconductors 51 Figure 29. NAND_DQS/NAND_DQ read valid window For DDR Source Synchronous mode, Figure 29 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid window. The typical value of tDQSQ is 0.85 ns (max) and 1 ns (max) for tQHS at 200 MB/s. GPMI will sample NAND_DATA[7:0] at both rising and falling edge of an delayed NAND_DQS signal, which can be provided by an internal DPLL. The delay value can be controlled by GPMI register GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX 8M Nano Applications Processor Reference Manual [IMX8MNRM]). Generally, the typical delay value of this register is equal to 0x7 which means 1/4 clock cycle delay expected. But if the board delay is big enough and cannot be ignored, the delay value should be made larger to compensate the board delay. Table 40. Source Synchronous mode timing parameters1 1 GPMI’s Source Synchronous mode output timing can be controlled by the module’s internal registers GPMI_TIMING2_CE_DELAY,GPMI_TIMING_PREAMBLE_DELAY,GPMI_TIMING2_POST_DELAY.ThisACtimingdepends on these registers settings. In the table, CE_DELAY/PRE_DELAY/POST_DELAY represents each of these settings. ID Parameter Symbol Timing T = GPMI Clock Cycle Unit Min. Max. NF18 NAND_CE0_B access time tCE CE_DELAY T - 0.79 [see note2] 2 T = tCK(GPMI clock period) –0.075 ns (half of maximum p-p jitter). ns NF19 NAND_CE0_B hold time tCH 0.5 tCK - 0.63 [see note2]ns NF20 Command/address NAND_DATAxx setup time tCAS 0.5 tCK - 0.05 ns NF21 Command/address NAND_DATAxx hold time tCAH 0.5 tCK - 1.23 ns NF22 clock period tCK — ns NF23 preamble delay tPRE PRE_DELAY T - 0.29 [see note2]ns NF24 postamble delay tPOST POST_DELAY T - 0.78 [see note2]ns NF25 NAND_CLE and NAND_ALE setup time tCALS 0.5 tCK - 0.86 ns NF26 NAND_CLE and NAND_ALE hold time tCALH 0.5 tCK - 0.37 ns NF27 NAND_CLK to first NAND_DQS latching transition tDQSS T - 0.41 [see note2]ns NF28 Data write setup — 0.25 tCK - 0.35 NF29 Data write hold — 0.25 tCK - 0.85 NF30 NAND_DQS/NAND_DQ read setup skew — — 2.06 NF31 NAND_DQS/NAND_DQ read hold skew — — 1.95 D0 D1 D2 D3 NF30 NF31 NF30 NF31 |
Codice articolo simile - IMX8MNCEC |
|
Descrizione simile - IMX8MNCEC |
|
|
Link URL |
Privacy Policy |
ALLDATASHEETIT.COM |
Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |