IMX8MNCEC datasheet(37/89 Pages) NXP

Il numero della parte	IMX8MNCEC

Spiegazioni elettronici	i.MX 8M Nano Applications Processor Datasheet for Consumer Products

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Electrical characteristics

i.MX 8M Nano Applications Processor Datasheet for Consumer Products, Rev. 0.1, 03/2020

NXP Semiconductors

37

3.9.2

Ultra-high-speed SD/SDIO/MMC host interface (uSDHC) AC

timing

This section describes the electrical information of the uSDHC, which includes SD/eMMC 5.1 (single data

rate) timing, eMMC 5.1/SD3.0 (dual data rate) AC timing, and SDR50/SDR104 AC timing.

3.9.2.1

SD/eMMC5.1 (single data rate) AC timing

Figure 12 depicts the timing of SD3.0/eMMC5.1 (SDR), and Table 31 lists the SD3.0/eMMC5.1 (SDR)

timing characteristics.

Figure 12. SD3.0/eMMC5.1 (SDR) timing

Table 31. SD3.0/eMMC5.1 (SDR) interface timing specification

ID

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

Clock Frequency (Low Speed)

fPP

1

0

400

kHz

Clock Frequency (SD/SDIO Full Speed/High Speed)

fPP

2

0

25/50

MHz

Clock Frequency (MMC Full Speed/High Speed)

fPP

3

0

20/52

MHz

Clock Frequency (Identification Mode)

fOD

100

400

kHz

SD2

Clock Low Time

tWL

7—

ns

SD3

Clock High Time

tWH

7—

ns

SD4

Clock Rise Time

tTLH

—3

ns

SD5

Clock Fall Time

tTHL

—3

ns

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)

SD6

uSDHC Output Delay

tOD

6.6

3.6

ns

SD1

SD3

SD5

SD4

SD7

SDx_CLK

SD2

SD8

SD6

Output from uSDHC to card

Input from card to uSDHC

SDx_DATA[7:0]

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