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IMX8MNIEC Scheda tecnica(PDF) 61 Page - NXP Semiconductors

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Spiegazioni elettronici  i.MX 8M Nano Applications Processor Datasheet for Industrial Products
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Electrical characteristics
i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 0.1, 03/2020
NXP Semiconductors
61
3.9.9.2.2
DDR mode
Figure 40. FlexSPI output timing in DDR mode
3.9.10 SAI/I2S switching specifications
This section provides the AC timings for the SAI in Master (clocks driven) and Slave (clocks input) modes.
All timings are given for non inverted serial clock polarity (SAI_TCR[TSCKP] = 0, SAI_RCR[RSCKP]
= 0) and non inverted frame sync (SAI_TCR[TFSI] = 0, SAI_RCR[RFSI] = 0). If the polarity of the clock
and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal
(SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below.
Table 52. FlexSPI output timing in DDR mode
Symbol
Parameter
Min.
Max.
Unit
[D:] Frequency of operation1
1 The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. See the
FlexSPI SDR input timing specifications.
TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1 register, the
default values are shown above. See the i.MX 8M Nano Applications
Processor Reference Manual (IMX8MNRM) for more details.
—166
MHz
TCK
[D:] SCK clock period
6.02
ns
TDSO
[D:] Output data setup time
0.6
ns
TDHO
[D:] Output data hold time
0.6
ns
TCSS
[D:] Chip select output setup time
3 x TCK - 1.075
ns
TCSH
[D:] Chip select output hold time
3 x TCK - 1.075
ns
Table 53. Master mode SAI timing (50 MHz)1
Num
Characteristic
Min
Max
Unit
S1
SAI_MCLK cycle time
20
ns
S2
SAI_MCLK pulse width high/low
40%
60%
MCLK period
S3
SAI_BCLK cycle time
20
ns
TCSS
TCK
TDVO
TDHO
TDVO
TDHO
TCSH
SCK
CS
SIO[0:7]


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