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PCA9450 Scheda tecnica(PDF) 40 Page - NXP Semiconductors |
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PCA9450 Scheda tecnica(HTML) 40 Page - NXP Semiconductors |
40 / 96 page NXP Semiconductors PCA9450 Power management IC for i.MX 8M application processor family PCA9450 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2019. All rights reserved. Product data sheet Rev. 1.0 — 19 November 2019 40 / 96 0x13 – BUCK2CTRL Reset Type O Bit Name Type Reset Description 1:0 B2_ENMODE R/W 10 BUCK2 enable mode 00b = OFF 01b = ON by PMIC_ON_REQ = H 10b = ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L 11b = Always ON 8.2.20 0x14 BUCK2OUT_DVS0 BUCK2 DVS output voltage at PMIC_STBY_REQ = L Table 40. 0x14 BUCK2OUT_DVS0 0x14 – BUCK2OUT_DVS0 Reset Type O Bit Name Type Reset Description 7 RSVD R/W 0 Reserved 6:0 B2_DVS0 R/W 001 0100 BUCK2 DVS0 Output voltage Programmable from 0.60 V to 2.1875 V in 12.5 mV step. Table 45 Default = 0.85 V 8.2.21 0x15 BUCK2OUT_DVS1 BUCK2 DVS output voltage at PMIC_STBY_REQ = H Table 41. 0x15 BUCK2OUT_DVS1 0x15 – BUCK2OUT_DVS1 Reset Type O Bit Name Type Reset Description 7 RSVD R/W 0 Reserved 6:0 B2_DVS1 R/W 001 0100 BUCK2 DVS1 Output voltage Programmable from 0.60 V to 2.1875 V in 12.5 mV step. Table 45 Default = 0.85 V 8.2.22 0x16 BUCK3CTRL BUCK3 control register for Ramp, DVS control, Active discharge, FPWM and Enable. The registers related to BUCK3 are only for PCA9450A. Table 42. 0x16 BUCK3CTRL 0x16 – BUCK3CTRL Reset Type O Bit Name Type Reset Description 7:6 RAMP R/W 01 BUCK3 DVS speed 00b = 25 mV / 1 μs 01b = 25 mV / 2 μs 10b = 25 mV / 4 μs 11b = 25 mV / 8 μs 5 RSVD R/W 0 Reserved |
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