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TLP719 Scheda tecnica(PDF) 4 Page - Toshiba Semiconductor |
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TLP719 Scheda tecnica(HTML) 4 Page - Toshiba Semiconductor |
4 / 5 page TLP719 2003-09-5 4 Switching Characteristics (Ta = 25°C, Vcc = 5V) Characteristic Symbol Test Cir- cuit Test Condition Min. Typ. Max. Unit Propagation delay time (H? L) tpHL IF = 0? 16mA RL = 1.9kO ? ? 0.8 µs Propagation delay time (L? H) tpLH Fig1 IF = 16? 0mA RL = 1.9kO ? ? 0.8 µs Common mode transient immunity at logic high output (Note 7) CMH IF = 0mA , VCM = 400Vp−p RL = 1.9kO 10000 ? ? V / µs Common mode transient immunity at logic low output (Note 7) CML Fig2 IF = 16mA , VCM = 400Vp−p RL = 1.9kO −10000 ? ? V / µs (Note 7) : CML is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic low state(VO < 0.8V). CMH is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic high state(VO >2V). Fig 1.Switching Time Test Circuit Fig 2.Common Mode Noise Immunity Test Circuit. Vcc=5V VO RL 1 2 3 5 4 6 IF MONITORING NODE MONITORING NODE PULSE INPUT (PW=100 µs Duty=10%) 0.1 µF tpLH tpHL 5V 1.5V Vo IF VOL IF → 10% tr 90% tf CMH 2V 0.8V VOL SW:A ( IF=16mA ) 400V VCM RL=1.9kΩ Vo Vcc=5V VCM 0V 0.1µF 1 2 3 5 4 6 + - SW B A → IF VOH SW:B ( IF=0mA ) CML CMH= tr (µs) 320 (V) CML= - tf (µs) 320 (V) |
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