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TLE75602-ESD Scheda tecnica(PDF) 49 Page - Infineon Technologies AG |
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TLE75602-ESD Scheda tecnica(HTML) 49 Page - Infineon Technologies AG |
49 / 70 page Datasheet 49 Rev. 1.0 2017-11-23 TLE75602-ESD SPIDER+ 12V Serial Peripheral Interface (SPI) 10 Serial Peripheral Interface (SPI) The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CSN. Data is transferred by the lines SI and SO at the rate given by SCLK. The falling edge of CSN indicates the beginning of an access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CSN. A modulo 8/16 counter ensures that data is taken only when a multiple of 8 bit has been transferred after the first 16 bits. Otherwise a TER bit is asserted. In this way the interface provides daisy chain capability with 16 bit as well as with 8 bit SPI devices. Figure 26 Serial Peripheral Interface 10.1 SPI Signal Description CSN - Chip Select The system microcontroller selects the TLE75602-ESD by means of the CSN pin. Whenever the pin is in “low” state, data transfer can take place. When CSN is in "high" state, any signals at the SCLK and SI pins are ignored and SO is forced into a high impedance state. CSN “high” to “low” Transition • The requested information is transferred into the shift register. • SO changes from high impedance state to "high" or “low” state depending on the logic OR combination between the transmission error flag (TER) and the signal level at pin SI. This allows to detect a faulty transmission even in daisy chain configuration. • If the device is in Sleep mode, SO pin remains in high impedance state and no SPI transmission occurs. Figure 27 Combinatorial Logic for TER bit 14 13 12 11 14 13 12 11 MSB MSB SPI _16bit.emf LSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 10 9 8 10 9 8 7 7 SO SI CSN SCLK time SPI _TER.emf SI SPI OR TER 0 1 SO CSN SCLK S SO S SI |
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