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TLE8110ED Scheda tecnica(PDF) 43 Page - Infineon Technologies AG |
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TLE8110ED Scheda tecnica(HTML) 43 Page - Infineon Technologies AG |
43 / 74 page Data Sheet 43 Rev. 1.0 2018-03-07 TLE8110ED Smart Multichannel Low Side Switch with Parallel Control and SPI Interface Control of the device 12.2.2 Daisy Chain The SPI-Interface of TLE8110ED provides daisy chain capability, see Chapter 12.2.3.4 for more details. In this configuration several devices are activated by the same S_CS signal. The S_SI line of one device is connected with the S_SO line of another device (see Figure 26), which builds a chain. The ends of the chain are connected with the output and input of the master device, S_SO and S_SI respectively. The master device provides the master clock CLK, which is connected to the S_CLK line of each device in the chain. By each clock edge on S_CLK, one bit is shifted into the S_SI. The bit shifted out can be seen at SO. After 16 S_CLK cycles, the data transfer for one device has been finished. In single chip configuration, the S_CS line must go high to make the device accept the transferred data. In daisy chain configuration the data shifted out at device 1 has been shifted in to device 2. Example: When using three devices in daisy chain, three times 16 bits have to be shifted through the devices. After that, the S_CS line must go high (see Figure 26). Figure 26 Principle example for Data Transfer in Daisy Chain Configuration Note: Due to the integrated modulo 8 counter, 8 bit and 16 bit devices can be used in one daisy chain. 12.2.3 SPI Protocol The device contains two protocol styles which are applied dependent of the used commands. There is the standard 16-bit protocol and the 2x8-bit protocol. Both protocols can appear also be mixed. 12.2.3.1 16-bit protocol Each cycle where a serial data or command frame is sent to the S_SI of the SPI interface, a data frame is returned at the same time by the S_SO. The content of the S_SO frame is dependent on the previous command which has been sent to S_SI. Read Command (R/W = R) returns one cycle later the content of the address register (see Figure 27). Figure 27 16-bit protocol SI SO CS CLK SI device 3 SI device 2 SI device 1 SO device 3 SO device 2 SO device 1 time SPI_DasyChain2.emf R ADR / DATA W ADR / DATA ADR / DATA R dept. of previous R/W Register Short Diagnosis* S_SO SPI_Protocol_Normal_Mode.vsd * dependent on ADR; In case CMD or DCC is addressed, related content. |
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