MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

1

REV 0

3/98

Dual D-Type Flip-Flop

with Set and Reset

The MC74VHCT74A is an advanced high speed CMOS D–type flip–flop

fabricated with silicon gate CMOS technology. It achieves high speed

operation similar to equivalent Bipolar Schottky TTL while maintaining

CMOS low power dissipation.

The signal level applied to the D input is transferred to Q output during the

positive going transition of the Clock pulse.

Reset (RD) and Set (SD) are independent of the Clock (CP) and are

accomplished by setting the appropriate input Low.

The internal circuit is composed of three stages, including a buffer output

which provides high noise immunity and stable output. The inputs tolerate

voltages up to 7V, allowing the interface of 5V systems to 3V systems.

The VHCT inputs are compatible with TTL levels. This device can be used

as a level converter for interfacing 3.3V to 5.0V, because it has full 5V CMOS

level output swings.

The VHCT74A input structures provide protection when voltages between

0V and 5.5V are applied, regardless of the supply voltage. The output

structures also provide protection when VCC=0V. These input and output

structures help prevent device destruction caused by supply voltage –

input/output voltage mismatch, battery backup, hot insertion, etc.

• High Speed: fmax = 60MHz (Typ) at VCC = 5V

• Low Power Dissipation: ICC = 2µA (Max) at TA = 25°C

• Power Down Protection Provided on Inputs

• Balanced Propagation Delays

• Designed for 4.5V to 5.5V Operating Range

• Low Noise: VOLP = 0.8V (Max)

• Pin and Function Compatible with Other Standard Logic Families

• Latchup Performance Exceeds 300mA

• ESD Performance: HBM > 2000V; Machine Model > 200V

• Chip Complexity: 128 FETs or 32 Equivalent Gates

LOGIC DIAGRAM

RD1

D1

CP1

SD1

RD2

D2

CP2

SD2

1

2

3

4

13

12

11

10

5

6

9

8

Q1

Q1

Q2

Q2

FUNCTION TABLE

Inputs

Outputs

SD

RD

CP

D

Q

Q

LH

X

X

HL

HL

X

X

LH

L

L

X

X

H*

H*

HH

H

H

L

HH

L

L

H

H

H

L

X

No Change

H

H

H

X

No Change

H

H

X

No Change

* Both outputs will remain high as long as Set and Reset are low, but the output

states are unpredictable if Set and Reset go high simultaneously.

MC74VHCT74A

PIN ASSIGNMENT

SD1

CP1

D1

RD1

11

12

13

14

8

9

10

5

4

3

2

1

7

6

SD2

CP2

D2

RD2

VCC

Q2

Q2

GND

Q1

Q1

D SUFFIX

14–LEAD SOIC PACKAGE

CASE 751A–03

DT SUFFIX

14–LEAD TSSOP PACKAGE

CASE 948G–01

ORDERING INFORMATION

MC74VHCTXXAD

MC74VHCTXXADT

MC74VHCTXXAM

SOIC

TSSOP

SOIC EIAJ

M SUFFIX

14–LEAD SOIC EIAJ PACKAGE

CASE 965–01