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EP2AGX45DF25I5 Scheda tecnica(PDF) 79 Page - Altera Corporation

Il numero della parte EP2AGX45DF25I5
Spiegazioni elettronici  Arria II Device Handbook
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Produttore elettronici  ALTERA [Altera Corporation]
Homepage  http://www.altera.com
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EP2AGX45DF25I5 Scheda tecnica(HTML) 79 Page - Altera Corporation

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Chapter 1: Device Datasheet for Arria II Devices
1–71
Switching Characteristics
December 2013
Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
Table 1–63 lists the memory output clock jitter specifications for Arria II GZ devices.
Duty Cycle Distortion (DCD) Specifications
Table 1–64 lists the worst-case DCD specifications for Arria II GX devices.
Table 1–65 lists the worst-case DCD specifications for Arria II GZ devices.
Table 1–63. Memory Output Clock Jitter Specification for Arria II GZ Devices (Note 1), (2), (3)
Parameter
Clock
Network
Symbol
–3
–4
Unit
Min
Max
Min
Max
Clock period jitter
Regional
t
JIT(per)
-55
55
-55
55
ps
Cycle-to-cycle period jitter
Regional
t
JIT(cc)
-110
110
-110
110
ps
Duty cycle jitter
Regional
t
JIT(duty)
-82.5
82.5
-82.5
82.5
ps
Clock period jitter
Global
t
JIT(per)
-82.5
82.5
-82.5
82.5
ps
Cycle-to-cycle period jitter
Global
t
JIT(cc)
-165
165
-165
165
ps
Duty cycle jitter
Global
t
JIT(duty)
-90
90
-90
90
ps
Notes to Table 1–63:
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.
(2) The clock jitter specification applies to memory output clock pins generated using differential signal-splitter and DDIO circuits clocked by a
PLL output routed on a regional or global clock network as specified. Altera recommends using regional clock networks whenever possible.
(3) The memory output clock jitter stated in Table 1–63 is applicable when an input jitter of 30 ps is applied.
Table 1–64. Duty Cycle Distortion on I/O Pins for Arria II GX Devices (Note 1)
Symbol
C4
I3, C5, I5
C6
Unit
Min
Max
Min
Max
Min
Max
Output Duty Cycle
45
55
45
55
45
55
%
Note to Table 1–64:
(1) The DCD specification applies to clock outputs from the PLL, global clock tree, IOE driving dedicated, and general
purpose I/O pins.
Table 1–65. Duty Cycle Distortion on I/O Pins for Arria II GZ Devices (Note 1)
Symbol
C3, I3
C4, I4
Unit
Min
Max
Min
Max
Output Duty Cycle
45
55
45
55
%
Note to Table 1–65:
(1) The DCD specification applies to clock outputs from the PLL, global clock tree, IOE driving dedicated, and general
purpose I/O pins.


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