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FAN6520A Scheda tecnica(PDF) 8 Page - Fairchild Semiconductor |
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FAN6520A Scheda tecnica(HTML) 8 Page - Fairchild Semiconductor |
8 / 15 page 8 REV. 1.0.2 8/26/04 FAN6520A PRODUCT SPECIFICATION Feedback Compensation Figure 7 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the reference voltage level. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the SW node. The PWM wave is smoothed by the output LC filter (LOUT and COUT). Figure 7. Voltage Mode Buck Converter Compensation Design The modulator transfer function is the small-signal transfer function of VOUT/VCOMP. This function is dominated by a DC Gain and the output filter (LOUT and COUT), with a double pole break frequency at FLC and a zero at FESR. The DC Gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage ∆VOSC. The following equations define the modulator break frequencies as a function of the output LC filter: 1. The compensation network consists of the error ampli- fier (internal to the FAN6520A) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (F0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at F0dB and 180 degrees. The equations below relate the compensation network’s poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 7. Use the following steps to locate the poles and zeros of the compensation network: 2. Pick gain (R2/R1) for the desired converter bandwidth. 3. Place 1st zero below the filter’s double pole (~75% FLC). 4. Place 2nd zero at filter’s double pole. 5. Place 1st pole at the ESR zero. 6. Place 2nd pole at half the switching frequency. 7. Check gain against the error amplifier’s open-loop gain. 8. Estimate phase margin. Repeat if necessary. Figure 8 shows an asymptotic plot of the DC-DC converter’s gain vs. frequency. The actual Modulator Gain has a high gain peak due to the high Q factor of the output filter and is not shown in Figure 8. Using the above guidelines should give a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabili- ties of the error amplifier. The Closed Loop Gain is con- structed on the graph of Figure 8 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function by the compensation transfer function and plotting the gain. The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with a –20dB/decade slope and a phase margin greater than 45°. Include worst case component variations when determining phase margin. Z FB COMP FB +VOUT Q2 L OUT COUT +5V VIN SW 0.8V ERROR AMP PWM OSC DETAILED COMPENSATION COMPONENTS COMP FB 0.8V ERROR AMP C1 R2 C3 R3 C2 R1 Z IN V OUT ZFB ZIN F LC 1 2 π LC × ------------------------- = (15) F ESR 1 2 π ESR × C × ------------------------------------ = (16) F Z1 1 2 πR 2C1 ---------------------- = (17) F P1 1 2 πR 2 C 1C2 C 1 C 2 + -------------------- ----------------------------------------- = (18) F Z2 1 2 πC 3 R1 R 3 + () ---------------------------------------- = (19) F P2 1 2 πR 3C3 ---------------------- = (20) |
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