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FAN5019B Scheda tecnica(PDF) 2 Page - Fairchild Semiconductor |
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FAN5019B Scheda tecnica(HTML) 2 Page - Fairchild Semiconductor |
2 / 30 page FAN5019B PRODUCT SPECIFICATION 2 REV. 1.0.0 Jul/15/05 Pin Assignments Pin Definitions Pin Number Pin Name Pin Function Description 1–5 VID [4:0] VID inputs. Determines the output voltage via the internal DAC. These inputs comply to VRM10/VRD10 specifications for static and dynamic operation. All have internal pull-ups (1.25V for VRM10 and 2.5V for VRM9) so leaving them open results in logic high. Leaving VID[4:0] open results in a "No CPU" condition disabling the PWM outputs. 6 VID5/SEL VID5 Input/DAC Select. Dual function pin that is either the 12.5mV DAC LSB for VRM10 or selects the VRM9 DAC codes when forced higher than Vtblsel(VRM9) voltage. The truth table is as follows: VVID5/SEL held > Vtblsel(VRM9); VRM9 DAC table is selected (See Table 3) VViD5/SEL < Vtblsel(VRM10); VRM10 DAC table is selected (See Table 2) and VViD5/SEL pin is used as VID5 input. 7FBRTN Feedback Return. Error Amp and DAC reference point. 8FB Feedback Input. Inverting input for Error Amp this pin is used for external compensation. This pin can also be used to introduce DC offset voltage to the output. 9COMP Error Amp output. This pin is used for external compensation. 10 PWRGD Power Good output. This is an open-drain output that asserts when the output voltage is within the specified tolerance. It is expected to be pulled up to an external voltage rail. 11 EN Enable. Logic signal that enables the controller when logic high. 12 DELAY Soft-start and Current Limit Delay. An external resistor and capacitor sets the softstart ramp rate and the over-current latch off delay. 13 RT Switching Frequency Adjust. This pin adjusts the output PWM switching frequency via an external resistor. 14 RAMPADJ PWM Current Ramp Adjust. An external resistor to Vcc will adjust the amplitude of the internal PWM ramp. 15 ILIMIT Current Limit Adjust. An external resistor sets the current limit threshold for the regulator circuit. This pin is internally pulled low when EN is low or the UVLO circuit is active. It is also used to enable the drivers. DELAY VID4 VID3 VID2 VID1 VID0 COMP CSCOMP PWRGD EN CSSUM RT VCC SW2 SW3 PWM3 PWM4 PWM1 GND FBRTN ILIMIT FB CSREF RAMPADJ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 FAN5019B TSSOP-28 SW1 PWM2 SW4 VID5/SEL |
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Descrizione simile - FAN5019B |
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