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74ALVC14PW Scheda tecnica(PDF) 1 Page - NXP Semiconductors |
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74ALVC14PW Scheda tecnica(HTML) 1 Page - NXP Semiconductors |
1 / 16 page 1. General description The 74ALVC14 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74ALVC14 provides six inverting buffers with Schmitt-trigger action. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. 2. Features s Wide supply voltage range from 1.65 V to 3.6 V s 3.6 V tolerant inputs/outputs s CMOS low power consumption s Direct interface with TTL levels (2.7 V to 3.6 V) s Power-down mode s Unlimited input rise and fall times s Latch-up performance exceeds 250 mA s Complies with JEDEC standard: x JESD8-7 (1.65 V to 1.95 V) x JESD8-5 (2.3 V to 2.7 V) x JESD8-B/JESD36 (2.7 V to 3.6 V) s ESD protection: x HBM EIA/JESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V s Multiple package options 3. Quick reference data 74ALVC14 Hex inverting Schmitt trigger Rev. 03 — 15 February 2005 Product data sheet Table 1: Quick reference data Symbol Parameter Conditions Min Typ Max Unit tPHL, tPLH propagation delay nA to nY VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ - 2.9 - ns VCC = 2.5 V; CL = 30 pF; RL = 500 Ω - 2.2 - ns VCC = 2.7 V; CL = 50 pF; RL = 500 Ω - 2.8 - ns VCC = 3.3 V; CL = 50 pF; RL = 500 Ω - 2.4 - ns |
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