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MC1494 Scheda tecnica(PDF) 9 Page - ON Semiconductor |
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MC1494 Scheda tecnica(HTML) 9 Page - ON Semiconductor |
9 / 16 page MC1494 9 MOTOROLA ANALOG IC DEVICE DATA Figure 19, the “X” input zero and “Y” input zero will be at approximately 15 MHz and 7.0 MHz respectively. It should be noted that the MC1494 multiplies in the time domain, hence, its frequency response is found by means of complex convolution in the frequency (Laplace) domain. This means that if the “X” input does not involve a frequency, it is not necessary to consider the “X” side frequency response in the output product. Likewise, for the “Y” side. Thus, for applications such as a wideband linear AGC amplifier which has a DC voltage as one input, the multiplier frequency response has one zero and one pole. For applications which involve an AC voltage on both the “X” and “Y” side such as a balanced modulator, the product voltage response will have two zeros and one pole, hence, peaking may be present in the output. From this brief discussion, it is evident that for AC applications; (1) the value of resistors RX, RY and RL should be kept as small as possible to achieve maximum frequency response, and (2) it is possible to select a load resistor RL such that the dominant pole (RL, CO) cancels the input zero (RX, 3.5 pF or RY, 3.5 pF) to give a flat amplitude characteristic with frequency. This is shown in Figures 11 and 12. Examination of the frequency characteristics of the “X” and “Y” inputs will demonstrate that for wideband amplifier applications, the best tradeoff with frequency response and gain is achieved by using the “Y” input for the AC signal. For AC applications requiring bandwidths greater than those specified for the MC1494, two other devices are recommended. For modulator–demodulator applications, the MC1496 may be used up to 100 MHz. For wideband multiplier applications, the MC1495 (using small collector loads and AC coupling) can be used. Slew–Rate The MC1494 multiplier is not slew–rate limited in the ordinary sense that an op amp is. Since all the signals in the multiplier are currents and not voltages, there is no charging and discharging of stray capacitors and thus no limitations beyond the normal device limitataions. However, it should be noted that the quiescent current in the output transistors is 0.5 mA and thus the maximum rate of change of the output voltage is limited by the output load capacitance by the simple equation: ∆VO C IO ∆T Slew Rate ∆VO = Thus, if CO is 10 pF, the maximum slew rate would be: ∆T = 0.5 x 10–3 10 x 10–12 = 50 V/µs This can be improved, if necessary, by the addition of an emitter–follower or other type of buffer. Phase Vector Error All multipliers are subject to an error which is known as the phase vector error. This error is a phase error only and does not contribute an amplitude error per se. The phase vector error is best explained by an example. If the “X” input is described in vector notation as; X= A ë0° and the “Y” input is described as; Y= B ë0° then the output product would be expected to be; VO= ABë0° (see Figure 20) However, due to a relative phase shift between the ‘‘X’’ and ‘‘Y’’ channels, the output product will be given by: VO = ABëφ Notice that the magnitude is correct but the phase angle of the product is in error. The vector (V) associated with this error is the ‘‘phase vector error’’. The startling fact about the phase vector error is that it occurs and accumulates much more rapidly than the amplitude error associated with frequency response. In fact, a relative phase shift of only 0.57 ° will result in a 1% phase vector error. For most applications, this error is X = A ë 0° Y = B ë V φ Figure 20. Phase Vector Error 0 ° AB ë φ AB ë0° meaningless. If phase of the output product is not important, then neither is the phase vector error. If phase is important, such as in the case of double sideband modulation or demodulation, then a 1% phase vector error will represent a 1% amplitude error a the phase angle of interest. Circuit Layout If wideband operation is desired, careful circuit layout must be observed. Stray capacitance across RX and RY should be avoided to minimize peaking (caused by a zero created by the parallel RC circuit). DC APPLICATIONS Squaring Circuit If the two inputs are connected together, the resultant function is squaring: VO = KV2 where K is the scale factor (see Figure 21). However, a more careful look at the multiplier’s defining equation will provide some useful information. The output voltage, without initial offset adjustments is given by: VO = K(VX + Viox –VX off) (VY + Vioy –VY off) + VOO (Refer to “Definitions” section for an explanation of terms.) With VX = VY = V (squaring) and defining; ∈x = Viox – Vx (off) ∈y = Vioy – Vy (off) The output voltage equation becomes: VO = KVx2+ KVx (∈x + ∈y) + K∈x ∈y + VOO |
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