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MC14517 Scheda tecnica(PDF) 4 Page - ON Semiconductor

Il numero della parte MC14517
Spiegazioni elettronici  Dual 64-Bit Static Shift Register
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SWITCHING CHARACTERISTICS (6.) (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
VDD
Min
Typ (7.)
Max
Unit
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.65 ns/pF) CL + 9.5 ns
tTLH, tTHL
5.0
10
15
100
50
40
200
100
80
ns
Propagation Delay Time
tPLH, tPHL = (1.7 ns/pF) CL + 390 ns
tPLH, tPHL = (0.66 ns/pF) CL + 177 ns
tPLH, tPHL = (0.5 ns/pF) CL + 115 ns
tPLH, tPHL
5.0
10
15
475
210
140
770
300
215
ns
Clock Pulse Width
tWH
5.0
10
15
330
125
100
170
75
60
ns
Clock Pulse Frequency
fcl
5.0
10
15
3.0
6.7
8.3
1.5
4.0
5.3
MHz
Clock Pulse Rise and Fall Time
tTLH, tTHL
5.0
10
15
See Note (8.)
Data to Clock Setup Time
tsu
5.0
10
15
0
10
15
– 40
– 15
0
ns
Data to Clock Hold Time
th
5.0
10
15
150
75
35
75
25
10
ns
Write Enable to Clock Setup Time
tsu
5.0
10
15
400
200
110
170
65
50
ns
Write Enable to Clock Release Time
trel
5.0
10
15
380
180
100
160
55
40
ns
6. The formulas given are for the typical characteristics only at 25
_C.
7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
8. When shift register sections are cascaded, the maximum rise and fall time of the clock input should be equal to or less than the rise and fall
time of the data outputs, driving data inputs, plus the propagation delay of the output driving stage.
Figure 1. Power Dissipation Test Circuit and Waveform
CL
CL
CL
CL
CL
CL
CL
CL
VDD
Q16 Q32 Q48 Q64
Q16 Q32 Q48 Q64
VDD
VDD
VSS
VSS
D
C
WE
D
C
WE
VSS
ID
D
C
50
µF
REPETITIVE WAVEFORM
C
D
fo
(f = 1/2 fo)


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