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CS5463-IS Scheda tecnica(PDF) 11 Page - Cirrus Logic |
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CS5463-IS Scheda tecnica(HTML) 11 Page - Cirrus Logic |
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11 / 44 page  CS5463 DS678PP1 11 SWITCHING CHARACTERISTICS • Min / Max characteristics and specifications are guaranteed over all Operating Conditions. • Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C. • VA+ = 5 V ±5% VD+ = 3.3 V ±5% or 5 V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V. • Logic Levels: Logic 0 = 0 V, Logic 1 = VD+. Notes: 16. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF. 17. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source. Parameter Symbol Min Typ Max Unit Rise Times Any Digital Input Except SCLK (Note 16) SCLK Any Digital Output trise - - - - - 50 1.0 100 - µs µs ns Fall Times Any Digital Input Except SCLK (Note 16) SCLK Any Digital Output tfall - - - - - 50 1.0 100 - µs µs ns Start-up Oscillator Start-up Time XTAL = 4.096 MHz (Note 17) tost -60- ms Serial Port Timing Serial Clock Frequency SCLK - - 2 MHz Serial Clock Pulse Width High Pulse Width Low t1 t2 200 200 - - - - ns ns SDI Timing CS Falling to SCLK Rising t3 50 - - ns Data Set-up Time Prior to SCLK Rising t4 50 - - ns Data Hold Time After SCLK Rising t5 100 - - ns SDO Timing CS Falling to SDI Driving t6 -20 50 ns SCLK Falling to New Data Bit (hold time) t7 -20 50 ns CS Rising to SDO Hi-Z t8 -20 50 ns Auto-Boot Timing Serial Clock Pulse Width Low Pulse Width High t9 t10 8 8 MCLK MCLK MODE setup time to RESET Rising t11 50 ns RESET rising to CS falling t12 48 MCLK CS falling to SCLK rising t13 100 8 MCLK SCLK falling to CS rising t14 16 MCLK CS rising to driving MODE low (to end auto-boot sequence). t15 50 ns SDO guaranteed setup time to SCLK rising t16 100 ns |
Codice articolo simile - CS5463-IS |
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Descrizione simile - CS5463-IS |
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