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MC140XXBD Scheda tecnica(PDF) 1 Page - ON Semiconductor

Il numero della parte MC140XXBD
Spiegazioni elettronici  CMOS SSI
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© Semiconductor Components Industries, LLC, 2005
February, 2005 − Rev. 5
1
Publication Order Number:
MC14070B/D
MC14070B, MC14077B
CMOS SSI
Quad Exclusive “OR” and “NOR” Gates
The MC14070B quad exclusive OR gate and the MC14077B quad
exclusive NOR gate are constructed with MOS P−channel and
N−channel enhancement mode devices in a single monolithic
structure. These complementary MOS logic gates find primary use
where low power dissipation and/or high noise immunity is desired.
Features
Supply Voltage Range = 3.0 Vdc to 18 Vdc
All Outputs Buffered
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
Double Diode Protection on All Inputs
MC14070B − Replacement for CD4030B and CD4070B Types
MC14077B − Replacement for CD4077B Type
Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
− 0.5 to +18.0
V
Vin, Vout
Input or Output Voltage Range
(DC or Transient)
− 0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
− 55 to +125
°C
Tstg
Storage Temperature Range
− 65 to +150
°C
TL
Lead Temperature
(8−Second Soldering)
260
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
MARKING
DIAGRAMS
1
14
PDIP−14
P SUFFIX
CASE 646
MC140xxBCP
AWLYYWW
SOIC−14
D SUFFIX
CASE 751A
1
14
140xxB
AWLYWW
xx
= Specific Device Code
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W
= Work Week
SOEIAJ−14
F SUFFIX
CASE 965
1
14
MC140xxB
AWLYWW
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
ORDERING INFORMATION


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