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MC14022BDR2 Scheda tecnica(PDF) 4 Page - ON Semiconductor |
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MC14022BDR2 Scheda tecnica(HTML) 4 Page - ON Semiconductor |
4 / 8 page MC14022B http://onsemi.com 4 SWITCHING CHARACTERISTICS (6.) (CL = 50 pF, TA = 25_C) Characteristic Symbol VDD Vdc Min Typ (7.) Max Unit Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns tTLH, tTHL 5.0 10 15 — — — 100 50 40 200 100 80 ns Propagation Delay Time Reset to Decode Output tPLH, tPHL = (1.7 ns/pF) CL + 415 ns tPLH, tPHL = (0.66 ns/pF) CL + 197 ns tPLH, tPHL = (0.5 ns/pF) CL + 150 ns tPLH, tPHL 5.0 10 15 — — — 500 230 175 1000 460 350 ns Propagation Delay Time Clock to Cout tPLH, tPHL = (1.7 ns/pF) CL + 315 ns tPLH, tPHL = (0.66 ns/pF) CL + 142 ns tPLH, tPHL = (0.5 ns/pF) CL + 100 ns tPLH, tPHL 5.0 10 15 — — — 400 175 125 800 350 250 ns Propagation Delay Time Clock to Decode Output tPLH, tPHL = (1.7 ns/pF) CL + 415 ns tPLH, tPHL = (0.66 ns/pF) CL + 197 ns tPLH, tPHL = (0.5 ns/pF) CL + 150 ns tPLH, tPHL 5.0 10 15 — — — 275 125 95 1000 460 350 ns Turn–Off Delay Time Reset to Cout tPLH = (1.7 ns/pF) CL + 315 ns tPLH = (0.66 ns/pF) CL + 142 ns tPLH = (0.5 ns/pF) CL + 100 ns tPLH 5.0 10 15 — — — 400 175 125 800 350 250 ns Clock Pulse Width tWH 5.0 10 15 250 100 75 125 50 35 — — — ns Clock Frequency fcl 5.0 10 15 — — — 5.0 12 16 2.0 5.0 6.7 MHz Reset Pulse Width tWH 5.0 10 15 500 250 190 250 125 95 — — — ns Reset Removal Time trem 5.0 10 15 750 275 210 375 135 105 — — — ns Clock Input Rise and Fall Time tTLH, tTHL 5.0 10 15 No Limit — Clock Enable Setup Time tsu 5.0 10 15 350 150 115 175 75 52 — — — ns Clock Enable Removal Time trem 5.0 10 15 420 200 140 260 100 70 — — — ns 6. The formulas given are for the typical characteristics only at 25 _C. 7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. |
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