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SN74AUP1G32DCKR Scheda tecnica(PDF) 2 Page - Texas Instruments |
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SN74AUP1G32DCKR Scheda tecnica(HTML) 2 Page - Texas Instruments |
2 / 15 page SN74AUP1G32 LOW POWER SINGLE 2INPUT POSITIVEOR GATE SCES580C – JUNE 2004 – REVISED JUNE 2005 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) This single 2-input positive-OR gate performs the Boolean function Y + A ) Bor Y + A • B in positive logic. NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING‡ NanoStar − WCSP (DSBGA) 0.23-mm Large Bump − YEP Reel of 3000 SN74AUP1G32YEPR _ _ _HG_ NanoFree − WCSP (DSBGA) 0.23-mm Large Bump − YZP (Pb-free) Reel of 3000 SN74AUP1G32YZPR _ _ _HG_ −40 °C to 85°C SOT (SOT-23) − DBV Reel of 3000 SN74AUP1G32DBVR H32_ −40 °C to 85°C SOT (SOT-23) − DBV Reel of 250 SN74AUP1G32DBVT H32_ SOT (SC-70) − DCK Reel of 3000 SN74AUP1G32DCKR HG_ SOT (SC-70) − DCK Reel of 250 SN74AUP1G32DCKT HG_ SOT (SOT-553) − DRL Reel of 4000 SN74AUP1G32DRLR HG_ † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). FUNCTION TABLE INPUTS OUTPUT A B OUTPUT Y L L L L HH H LH H H H logic diagram (positive logic) 1 2 4 A B Y |
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