MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

2–144

REV 6

9/96

4-Bit Differential ECL

Bus/TTL Bus Transceiver

The MC10H/100H680 is a dual supply 4–bit differential ECL bus to TTL

bus transceiver. It is designed to allow the system designer to no longer be

limited in bus speed associated with standard TTL busses. Using a

differential ECL Bus will increase the frequency of operation and increase

noise immunity.

Both the TTL and the ECL ports are capable of driving a bus. The ECL

outputs have the ability to drive 25

Ω, allowing both ends of the bus line to be

terminated in the characteristic impedance of 50

Ω. The TTL outputs are

specified to source 15 mA and sink 48 mA, allowing the ability to drive highly

capacitive loads.

The ECL output levels are VOH approximately equal to –1.0 V and VOL

cutoff equal to –2.0 V (VTT). When the ECL ports are disabled both EIOx and

EIOxB go to the VOL cutoff level. The ECL input receivers have special

circuitry which detects this disabled condition, prevents oscillation, and

forces the TTL output to the low state. The noise margin in this disabled state

is greater than 600 mV. Multiple ECL VCCO pins are utilized to minimize

switching noise.

The TTL ports have standard levels. The TTL input receivers have PNP

input devices to significantly reduce loading. Multiple TTL power and ground

pins are utilized to minimize switching noise.

The control pins (EDIR and ECEB) of the 10H version is compatible with

MECL 10H ECL logic levels. The control pins of the 100H version are

compatible with 100K levels.

• Differential ECL Bus (25 Ω) I/O Ports

• High Drive TTL Bus I/O Ports

• Extra TTL and ECL Power/Ground Pins to Minimize

Switching Noise

• Dual Supply

• Direction and Chip Enable Control Pins

Pinout: 28–Lead PLCC (Top View)

1

56

7

8

9

10

11

25

24

23

22

21

20

19

26

27

28

2

3

412

13

14

15

16

17

18

T101

GT2

VT1

GT1

TIO0

TDIR

EDIR

EIO3B

VCCO4

EIO3

VCCE

EIO2B

VCCO3

EIO2

PIN DESCRIPTIONS

Pin

Symbol

Function

1

GT1

TTL Ground 1

2

TIO0

TTL I/O Bit 0

3

TDIR

TTL Direction Control

4

EDIR

ECL Direction Control

5

EIO0

ECL I/O Bit 0

6

VCCO1

ECL VCC 1 (0V) – Outputs

7

EIO0B

ECL I/O Bit 0 Bar

8

VEE

ECL Supply (–5.2/–4.5V)

9

EIO1

ECL I/O Bit 1

10

VCCO2

ECL VCC 2 (0V) – Outputs

11

EIO1B

ECL I/O Bit 1 Bar

12

EIO2

ECL I/O Bit 2

13

VCCO3

ECL VCC 3 (0V) – Outputs

14

EIO2B

ECL I/O Bit 2 Bar

15

VCCE

ECL VCC (0V)

16

EIO3

ECL I/O Bit 3

17

VCCO4

ECL VCC 4 (0V) – Outputs

18

EIO3B

ECL I/O Bit 3 Bar

19

ECEB

ECL Chip Enable Bar Control

20

TCEB

TTL Chip Enable Bar Control

21

TIO3

TTL I/O Bit 3

22

GT4

TTL Ground 4

23

VT2

TTL Supply 2 (5V)

24

GT3

TTL Ground 3

25

TIO2

TTL I/O Bit 2

26

TIO1

TTL I/O Bit 1

27

GT2

TTL Ground 2

28

VT1

TTL Supply 1 (5V)

MC10H680

MC100H680

FN SUFFIX

PLASTIC PACKAGE

CASE 776–02