MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

2–316

REV 2

9/96

Hex ECL/TTL Transceiver

with Latches

The MC10/100H681 is a dual supply Hex ECL/TTL transceiver with

latches in both directions. ECL controlled Direction and Chip Enable Bar

pins. There are two Latch Enable pins, one for each direction.

The ECL outputs are single ended and drive 50

Ω. The TTL outputs are

specified to source 15 mA and sink 48 mA, allowing the ability to drive highly

capacitive loads. The high driving ability of the TTL outputs make the device

ideal for bussing applications.

The ECL output levels are standard VOH and VOL cutoff equal to –2.0 V

(VTT). When the ECL ports are disabled the outputs go to the VOL cutoff

level. Multiple ECL VCCO pins are utilized to minimize switching noise.

The TTL ports have standard levels. The TTL input receivers have PNP

input devices to significantly reduce loading. Multiple TTL power and ground

pins are utilized to minimize switching noise.

The 10H version is compatible with MECL 10H ECL logic levels. The

100H version is compatible with 100K levels.

• Separate Latch Enable Controls for each Direction

• ECL Single Ended 50 Ω I/O Port

• High Drive TTL I/O Ports

• Extra TTL and ECL Power/Ground Pins to Minimize

Switching Noise

• Dual Supply

• Direction and Chip Enable Control Pins

Pinout: 28–Lead PLCC (Top View)

1

56

78

9

10

11

25

24

23

22

21

20

19

26

27

28

2

3

4

12

13

14

15

16

17

18

TIO2

VT

GT

TIO1

VT

GT

TIO0

EIO5

VCCO

EIO4

VCCE

EIO3

VCCO

EIO2

Pin

Symbol

Description

1

TI01

TTL I/O BIT 1

1

2

TI01

VT

TTL I/O BIT 1

TTL VCC (5.0 V)

2

3

VT

GT

TTL VCC (5.0 V)

TTL GND (0 V)

3

4

GT

TI00

TTL GND (0 V)

TTL I/O Bit 0

4

5

TI00

DIR

TTL I/O Bit 0

Direction Control (ECL)

6

CEB

LEET

()

Chip Enable Bar Control (ECL)

L

h E

bl ECL TTL C

l (ECL)

7

8

LEET

LETE

p(

)

Latch Enable ECL-TTL Control (ECL)

L t h E

bl TTL ECL C

t l (ECL)

8

9

LETE

V

Latch Enable TTL-ECL Control (ECL)

ECL S

l ( 5 2 / 4 5 V)

9

10

VEE

EI00

ECL Supply (– 5.2 /– 4.5 V)

ECL I/O BIT 0

10

11

EI00

EI01

ECL I/O BIT 0

ECL I/O BIT 1

11

12

EI01

EI02

ECL I/O BIT 1

ECL I/O BIT 2

12

13

EI02

VCCO

ECL I/O BIT 2

ECL VCC (0 V) — Outputs

13

14

VCCO

EIO3

ECL VCC (0 V) — Outputs

TTL I/O BIT 3

14

15

EIO3

VCCE

TTL I/O BIT 3

ECL VCC (0 V)

15

16

VCCE

EIO4

ECL VCC (0 V)

ECL I/O BIT 4

16

17

EIO4

VCCO

ECL I/O BIT 4

ECL VCC (0 V) — Outputs

17

18

VCCO

EIO5

ECL VCC (0 V) — Outputs

ECL I/O BIT 5

18

19

EIO5

TI05

ECL I/O BIT 5

TTL I/O BIT 5

19

20

TI05

GT

TTL I/O BIT 5

TTL GND (0 V)

0

21

G

VT

G(0

)

TTL VCC (5.0 V)

22

23

TI04

GT

CC ()

TTL I/O BIT 4

TTL GND (0 V)

23

24

GT

VT

TTL GND (0 V)

TTL V

(5 0 V)

24

25

VT

TIO3

TTL VCC (5.0 V)

TTL I/O BIT 3

25

26

TIO3

TIO2

TTL I/O BIT 3

TTL I/O BIT 2

26

27

TIO2

VT

TTL I/O BIT 2

TTL VCC (5 0 V)

27

28

VT

GT

TTL VCC (5.0 V)

TTL VCC (0 V)

28

GT

TTL VCC (0 V)

MC10H681

MC100H681

FN SUFFIX

PLASTIC PACKAGE

CASE 776–02