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KM732V696L Scheda tecnica(PDF) 5 Page - Samsung semiconductor |
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KM732V696L Scheda tecnica(HTML) 5 Page - Samsung semiconductor |
5 / 16 page PRELIMINARY KM732V696/L 64Kx32 Synchronous SRAM Rev 1.0 - 5 - May 1997 SYNCHRONOUS TRUTH TABLE NOTE : 1. X means "Don ′t Care". 2. The rising edge of clock is symbolized by ↑. 3. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. 4. Operation finally depends on status of asynchronous input pins(ZZ and OE). CS1 CS2 CS2 ADSP ADSC ADV WRITE CLK Address Accessed Operation H X X X L X X ↑ N/A Not Selected L L X L X X X ↑ N/A Not Selected L X H L X X X ↑ N/A Not Selected L L X X L X X ↑ N/A Not Selected L X H X L X X ↑ N/A Not Selected L H L L X X X ↑ External Address Begin Burst Read Cycle L H L H L X L ↑ External Address Begin Burst Write Cycle L H L H L X H ↑ External Address Begin Burst Read Cycle X X X H H L H ↑ Next Address Continue Burst Read Cycle H X X X H L H ↑ Next Address Continue Burst Read Cycle X X X H H L L ↑ Next Address Continue Burst Write Cycle H X X X H L L ↑ Next Address Continue Burst Write Cycle X X X H H H H ↑ Current Address Suspend Burst Read Cycle H X X X H H H ↑ Current Address Suspend Burst Read Cycle X X X H H H L ↑ Current Address Suspend Burst Write Cycle H X X X H H L ↑ Current Address Suspend Burst Write Cycle WRITE TRUTH TABLE NOTE : 1. X means "Don ′t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK( ↑). GW BW WEa WEb WEc WEd Operation H H X X X X READ H L H H H H READ H L L H H H WRITE BYTE a H L H L H H WRITE BYTE b H L H H L L WRITE BYTE c and d H L L L L L WRITE ALL BYTEs L X X X X X WRITE ALL BYTEs ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2) : Operation ZZ OE I/O Status Sleep Mode H X High-Z Read L L DQ L H High-Z Write L X Din, High-Z Deselected L X High-Z TRUTH TABLES NOTE 1. X means "Don ′t Care". 2. ZZ pin is pulled down internally 3. For write cycles that following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 4. Sleep Mode means power down state of which stand-by current does not depend on cycle time. 5. Deselected means power down state of which stand-by current depends on cycle time. |
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