KM732V688 datasheet(7/15 Pages) SAMSUNG

Il numero della parte	KM732V688

Spiegazioni elettronici	64Kx32 Synchronous SRAM

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PRELIMINARY

Rev 2.0

KM732V688/L

64Kx32 Synchronous SRAM

- 7 -

Jun. 1998

DC ELECTRICAL CHARACTERISTICS

* VIL(Min) = -3.0(Pulse Width

≤20ns)

** In Case of I/O Pins, the Max. VIH=VDDQ + 0.5V

Parameter

Symbol

Test Conditions

Min

Max

Unit

Input Leakage Current(except ZZ)

IIL

VDD=VSS to VDD, VIN=VSS to VDD

-2

+2

µA

Output Leakage Current

IOL

Output Disabled,

VOUT=VSS to VDDQ

-2

+2

µA

Operating Current

ICC

Device Selected, IOUT=0mA,

ZZ

≤VIL, All Inputs=VIL or VIH

Cycle Time

≥tCYC Min

-13

-

250

mA

-15

-

220

Standby Current

ISB

Device deselected, IOUT=0mA, ZZ

≤VIL,

f=Max, All Inputs

≤0.2V or≥VDD-0.2V

-

60

mA

ISB1

Device deselected, IOUT=0mA,

ZZ

≤0.2V, f=0,

All Inputs=fixed( VDD-0.2V or

-

10

mA

L-Ver.

-

2.0

mA

ISB2

Device deselected, IOUT=0mA,

ZZ

≥VDD-0.2V, f=Max,

All Inputs

≤VIL or≥VIH

-

10

mA

L-Ver.

-

1

mA

Output Low Voltage

VOL

IOL=8.0mA

-

0.4

V

Output High Voltage

VOH

IOH=-4.0mA

2.4

-

V

Input Low Voltage

VIL

-0.5*

0.8

V

Input High Voltage

VIH

2.0

5.5**

V

(VDD=3.3V-5%/+10%, VDDQ=3.3V-5%/+10%, TA=0 to 70

°C)

TEST CONDITIONS

Parameter

Value

Input Pulse Level

0 to 3V

Input Rise and Fall Time(Measured at 0.3V and 2.7V)

2ns

Input and Output Timing Reference Levels

1.5V

Output Load

See Fig. 1

(TA=0 to 70

°C, VDD=3.3V-5%/+10%, VDDQ=3.3V-5%/+10%, unless otherwise specified)

Output Load(A)

Output Load(B)

(for tLZC, tLZOE, tHZOE& tHZC)

Dout

Z0=50

Ω

VL=1.5V

Dout

353

Ω

5pF*

+3.3V

319

Ω

* Capacitive Load consists of all components of

Fig. 1

30pF*

* Including Scope and Jig Capacitance

the test environment.

RL=50

Ω

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