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KMM5322204C2WG Scheda tecnica(PDF) 7 Page - Samsung semiconductor |
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KMM5322204C2WG Scheda tecnica(HTML) 7 Page - Samsung semiconductor |
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7 / 17 page  DRAM MODULE KMM5322204C2W/C2WG Rev. 0.0 (Nov. 1997) - 7 - NOTES An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. Measured with a load equivalent to 2 TTL loads and 100pF. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. Assumes that tRCD ≥tRCD(max). This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V OH or VOL. tWCS is non-restrictive operating parameter. It is included in the data sheet as electrical characteristic s only. If tWCS ≥tWCS(min), the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. Either tRCH or tRRH must be satisfied for a read cycle. These parameter are referenced to the CAS leading edge in early write cycles and to the W leading edge in read-write cycles. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. tCEZ(max), tREZ(max), tWEZ(max) and tOEZ(max) define the time at which the output achieves the open circuit condition and are not referenced to output voltage level. If RAS goes to high before CAS high going, the open circuit condtion of the output is achieved by CAS high going. If CAS goes to high before RAS high going, the open circuit condi- tion of the output is achieved by RAS high going. tASC ≥tCP min 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V, Output loading CL=100pF Parameter Symbol -5 -6 Unit Note Min Max Min Max Hyper page mode cycle time tHPC 25 30 ns 13 CAS precharge time(Hyper page cycle) tCP 8 10 ns RAS pulse width(Hyper page cycle) tRASP 50 200K 60 200K ns RAS hold time from CAS precharge tRHCP 30 35 ns W to RAS precharge time(C-B-R refresh) tWRP 10 10 ns W to RAS hold time(C-B-R refresh) tWRH 10 10 ns Output data hold time tDOH 5 5 ns Output buffer turn off delay from RAS tREZ 3 13 3 15 ns 6,11,12 Output buffer turn off delay from W tWEZ 3 13 3 15 ns 6,11 W to data delay tWED 15 15 ns W pulse width (Hyper Page Cycle) tWPE 5 5 ns AC CHARACTERISTICS (0 °C≤TA≤70°C, VCC=5.0V±10%. See notes 1,2.) 11. 12. 13. |
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