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CAT1320UI-25TSSOP Scheda tecnica(PDF) 5 Page - Catalyst Semiconductor |
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CAT1320UI-25TSSOP Scheda tecnica(HTML) 5 Page - Catalyst Semiconductor |
5 / 18 page 5 Advance Information CAT1320, CAT1321 Doc No. 25085, Rev. 00 RESET CIRCUIT A.C. CHARACTERISTICS Notes: 1. Test Conditions according to “AC Test Conditions” table. 2. Power-up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table 3. Power-Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table 4. VCC Glitch Reference Voltage = VTHmin; Based on characterization data 5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. 6. tPUR and tPUW are the delays required from the time VCC is stable until the specified memory operation can be initiated. AC TEST CONDITIONS RELIABILITY CHARACTERISTICS Symbol Parameter Reference Test Method Min Max Units NEND(1) Endurance MIL-STD-883, Test Method 1033 1,000,000 Cycles/Byte TDR(1) Data Retention MIL-STD-883, Test Method 1008 100 Years VZAP(1) ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts ILTH(1)(2) Latch-Up JEDEC Standard 17 100 mA s e g a t l o v e s l u p t u p n IV 2 . 0 C C V 8 . 0 o t C C s e m i t ll a f d n a e s i r t u p n Is n 0 1 s e g a t l o v e c n e r e f e r t u p n IV 3 . 0 C C V 7 . 0 , C C s e g a t l o v e c n e r e f e r t u p t u OV 5 . 0 C C d a o L t u p t u O I : e c r u o S t n e r r u C L O ; A m 3 = C L F p 0 0 1 = l o b m y Sr e t e m a r a P t s e T s n o i t i d n o C n i Mp y Tx a Ms t i n U t T S R U P t u o e m i T t e s e R2 e t o N0 3 10 0 20 7 2s m t D P R V H T y a l e D t u p t u o T E S E R o t3 e t o N5 s µ t H C T I L G V C C h t d i W e s l u P t c e j e R h c t il G5 , 4 e t o N0 3s n h c t il G R My t i n u m m I h c t il G t e s e R l a u n a M5 e t o N0 0 1s n t W R M h t d i W e s l u P R M5 e t o N5 s µ G N I M I T P U - R E W O P 6 , 5 l o b m y Sr e t e m a r a P t s e T s n o i t i d n o C n i Mp y Tx a Ms t i n U t R U P n o i t a r e p O d a e R o t p U - r e w o P 0 7 2s m t W U P n o i t a r e p O e t i r W o t p U - r e w o P 0 7 2s m Notes: 1. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested. 2. Latch-up protection is provided for stresses up to 100mA on input and output pins from -1V to VCC + 1V. |
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