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CAT1232LPGZ Scheda tecnica(PDF) 5 Page - Catalyst Semiconductor |
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CAT1232LPGZ Scheda tecnica(HTML) 5 Page - Catalyst Semiconductor |
5 / 9 page 5 CAT1232LP/CAT1832 Doc. No. 25089, Rev. A © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice APPLICATION INFORMATION SUPPLY VOLTAGE MONITOR Reset Signal Polarity and Output Stage Structure RESET is an active LOW signal. It is developed with an open drain driver in the CAT1232LP. A pull-up resistor is required, typical values are 10k Ω to 50kΩ. The CAT1832 uses a CMOS push-pull output stage for the RESET. RESET is an active High signal developed by a CMOS push-pull output stage and is the logical opposite to RESET. Trip Point Tolerance Selection The TOL input is used to select the VCC trip point threshold. This selection is made connecting the TOL input to ground or VCC. Connecting TOL to Ground makes the VCC trip threshold 4.62V for the CAT1232LP and 2.88V for the CAT1832. Connecting TOL to VCC makes the VCC trip threshold 4.37V for the CAT1232LP and 2.55V for the CAT1832. After VCC has risen above the trip point set by TOL, RESET and RESET remain active for a minimum time period of 250ms. On power-down, once VCC falls below the reset threshold the RESET outputs will remain active and are guaranteed valid down to a VCC level of 1.0V. e c n a r e l o T t c e l e S e g a t l o V t n i o P p i r T e c n a r e l o T ) V ( e g a t l o V t n i o P p i r T N I ML A N I M O NX A M P L 2 3 2 1 T A C V = L O T C C % 0 15 2 . 47 3 . 49 4 . 4 P L 2 3 2 1 T A C D N G = L O T % 50 5 . 42 6 . 44 7 . 4 2 3 8 1 T A C V = L O T C C % 0 27 4 . 25 5 . 24 6 . 2 2 3 8 1 T A C = L O TD N G % 0 10 8 . 28 8 . 27 9 . 2 Figure 1. Timing Diagram: Power Up Figure 2. Timing Diagram: Power Down VCCTP(MAX) VCCTP VCCTP(MIN) VCC RESET RESET tR tRPU VOH VOL VCCTP(MAX) VCCTP VCCTP(MIN) VCC RESET RESET tF VOH VOL tRPD Manual Reset Operation Push-button input, PBRST, allows the user to issue reset signals. The pushbutton input is debounced and is pulled high through an internal 40k Ω resistor. When PBRST is held low for the minimum time of 20 ms, both resets become active and remain active for a minimum time period of 250ms after PBRST returns high. No external pull-up resistor is required, since PBRST is pulled high by an internal 40k Ω resistor. PBRST can be driven from a TTL or CMOS logic line or short-ed to ground with a mechanical switch. |
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