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CAT24FC32AJTE13 Scheda tecnica(PDF) 9 Page - Catalyst Semiconductor |
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CAT24FC32AJTE13 Scheda tecnica(HTML) 9 Page - Catalyst Semiconductor |
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9 / 12 page  CAT24FC32A 9 Doc. No. 1048, Rev. F Figure 10. Page Write Timing been transmitted, CAT24FC32A will respond with an acknowledge, and internally increment the five low order address bits by one. The high order bits remain unchanged. If the Master transmits more than 32 bytes before sending the STOP condition, the address counter ‘wraps around’, and previously transmitted data will be overwritten. When all 32 bytes are received, and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the CAT24FC32A in a single write cycle. Acknowledge Polling Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write operation, CAT24FC32A initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If CAT24FC32A is still busy with the write operation, no ACK will be returned. If CAT24FC32A has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation. WRITE PROTECTION The Write Protection feature allows the user to protect against inadvertent programming of the memory array. If the WP pin is connected to VCC, the entire memory array is protected and becomes read only. The CAT24FC32A will accept both slave and byte addresses, but the memory location accessed is protected from programming by the device’s failure to send an acknowledge after the first byte of data is received. The WP input is sampled in the end of acknowledge pulse after second address byte, accordingly with setup and hold times relative to negative clock edge (Figure 2). READ OPERATIONS The READ operation for the CAT24FC32A is initiated in the same manner as the write operation with one exception, that R/W bit is set to one. Three different READ operations are possible: Immediate/Current Address READ, Selective/Random READ and Sequential READ. Immediate/Current Address Read The CAT24FC32A’s address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was Figure 11. Immediate Address Read Timing SCL SDA 8TH BIT STOP NO ACK DATA OUT 89 SLAVE ADDRESS S A C K BUS ACTIVITY: MASTER SDA LINE S T A R T N O A C K DATA S T O P P X=Don't care bit A15—A8 SLAVE ADDRESS S A C K A C K A C K BUS ACTIVITY: MASTER SDA LINE S T A R T A7—A0 BYTE ADDRESS DATA n+31 DATA A C K S T O P A C K DATA n A C K P A C K X XX X |
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