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TMP86FM29UG Scheda tecnica(PDF) 8 Page - Toshiba Semiconductor |
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TMP86FM29UG Scheda tecnica(HTML) 8 Page - Toshiba Semiconductor |
8 / 8 page TMP86FM29 2004-03-01 86FM29-6 Operational Description 1. CPU Core Functions The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, the external memory interface, and the reset circuit. 1.1 Memory Address Map The TMP86FM29 memory consists of 5 blocks: FLASH memory, BOOT ROM, RAM, DBR (Data buffer register) and SFR (Special function register). They are all mapped in 64-Kbyte address space. Figure 1.1.1 shows the TMP86FM29 memory address map. The general-purpose registers are not assigned to the RAM address space. Figure 1.1.1 Memory Address Maps 1.2 Program Memory (FLASH) The TMP86FM29 has a 32 K × 8 bits (Address 8000H to FFFFH) of Flash memory. FLASH memory: FLASH memory includes: FLASH memory Vector table BOOT ROM: FLASH writing program RAM: Random Access Memory includes: Data memory Stack SFR: Special Function Register includes: I/O ports Peripheral control registers Peripheral status registers System control registers Interrupt control registers Program Status Word DBR: Data Buffer Register includes: Peripheral control registers Peripheral Status registers Vector table for vector call instructions (16 vectors) Vector table for interrupts/reset (16 vectors) Vector table for interrupts (8 vectors) 0000H 64 bytes 1536 bytes 128 bytes SFR RAM DBR FLASH memory 32688 bytes 32 bytes 32 bytes 003FH 0040H 063FH 0F80H 0FFFH 8000H FFBFH FFC0H FFDFH FFE0H FFFFH 16 bytes FFB0H 2048 bytes BOOT ROM 3800H 3FFFH |
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