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SN74GTLPH1645 Scheda tecnica(PDF) 4 Page - Texas Instruments |
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SN74GTLPH1645 Scheda tecnica(HTML) 4 Page - Texas Instruments |
4 / 17 page www.ti.com FUNCTIONAL DESCRIPTION SN74GTLPH1645 16-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES290D – OCTOBER 1999 – REVISED JUNE 2005 The SN74GTLPH1645 is a high-drive (100-mA), 16-bit bus transceiver partitioned as two 8-bit segments and is designed for asynchronous communication between data buses. The device transmits data from the A port to the B port or from the B port to the A port, depending on the logic level at the direction-control (DIR) input. OE can be used to disable the device so the buses are effectively isolated. Data polarity is noninverting. For A-to-B data flow, when OE is low and DIR is high, the B outputs take on the logic value of the A inputs. When OE is high, the outputs are in the high-impedance state. The data flow for B to A is similar to A to B, except OE and DIR are low. FUNCTION TABLES <br/> OUTPUT CONTROL INPUTS OUTPUT MODE OE DIR H X Z Isolation L L B data to A port True transparent L H A data to B port B-PORT EDGE-RATE CONTROL (ERC) INPUT ERC OUTPUT B-PORT LOGIC NOMINAL EDGE RATE LEVEL VOLTAGE L GND Slow H VCC Fast 4 |
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