MPEG-4 Audiovisual Codec LSI

Preliminary

TC35273

TOSHIBA Confidential

2000-4-27

4/23

Version 0.90

1.2. System configuration.

Fig. 1 illustrates a block diagram of this LSI. Three signal processing core, peripheral interfaces,

and 12-Mbit DRAM are integrated in a single chip.

Bitstream input/output are performed via a network interface in the Mux/Demux core.

A Microphone and a speaker can be connected to a PCM interface in a speech/audio core via

external DAC and ADC.

TOSHIBA CMOS camera is connected to a camera interface via a camera DSP “TC90A50F” or

“TC90A70F”. NTSC camera is also connected via an NTSC decoder.

LCD or NTSC display is connected to an LCD interface via TOSHIBA LCD controller or an NTSC

encoder, respectively.

Host CPU is connected via a host interfaces. It downloads firmwares into the embedded DRAM

and accesses to internal registers.

Fig. 1 Block Diagram

12Mbit Embedded DRAM

Arbiter + DRAM Controller

Bitstream In/Out

Cam.

I/F

LCD

I/F

Pre-

filter

Host

I/F

DMA Controller

HW

RISC

HW

MPEG-4 Video

DMA Controller

HW

RISC

HW

Speech/Audio

DMA Controller

HW

RISC

HW

Mux./Demux.

D/A

A/D

LCDC

Camera

DSP

Host

CPU

Network Bitstream

Interface