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CAT24FC17 Scheda tecnica(PDF) 3 Page - Catalyst Semiconductor

Il numero della parte CAT24FC17
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CAT24FC17
3
Doc No. 1077, Rev. F
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Write Cycle Limits
Symbol
Parameter
Min
Typ
Max
Units
tWR
Write Cycle Time
5
ms
A.C. CHARACTERISTICS
VCC = 2.5 V to 5.5 V, unless otherwise specified.
Read & Write Cycle Limits
Symbol
Parameter
2.5 V - 5.5 V
Min
Max
Units
FSCL
Clock Frequenc
400
kHz
TI(1)
Noise Suppression Time Constant at SCL, SDA Inputs
100
ns
tAA
SCL Low to SDA Data Out and ACK Out
900
ns
tBUF(1)
Time the Bus Must be Free Before a New Transmission
1300
ns
Can Start
tHD:STA
Start Condition Hold Time
600
ns
tLOW
Clock Low Period
1300
ns
tHIGH
Clock High Period
600
ns
tSU:STA
Start Condition Setup Time
600
ns
(for a Repeated Start Condition)
tHD:DAT
Data In Hold Time
0
ns
tSU:DAT
Data In Setup Time
100
ns
tR(1)
SDA and SCL Rise Time
300
ns
tF(1)
SDA and SCL Fall Time
300
ns
tSU:STO
Stop Condition Setup Time
600
ns
tDH
Data Out Hold Time
100
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Power-Up Timing(1)(2)
Symbol
Parameter
Min
Typ
Max
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
1
ms
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.


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