ADV7330KST datasheet(10/76 Pages) AD

Il numero della parte	ADV7330KST

Spiegazioni elettronici	Multiformat 11-Bit Triple DAC Video Encoder

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Produttore elettronici	AD [Analog Devices]

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REV. B

–10–

ADV7330

HSYNC_I/P

BLANK_I/P

VSYNC_I/P

Y7–Y0

Cb

Y

Cr

Y

B

A

A = 32 CLK CYCLES FOR 525p

A = 24 CLK CYCLES FOR 626p

AS RECOMMENDED BY STANDARD

B (MIN) = 244 CLK CYCLES FOR 525p

B (MIN) = 264 CLK CYCLES FOR 625p

Figure 9. PS 4:2:2, 1

× 8-Bit Interleaved Input Timing Diagram

Y7–Y0

Cb

Y

Cr

Y

PAL = 264 CLK CYCLES

NTSC = 244 CLK CYCLES

*SELECTED BY ADDRESS 44h BIT 7

PAL = 24 CLK CYCLES

NTSC = 32 CLK CYCLES

BLANK_I/P

HSYNC_I/P

VSYNC_I/P

Figure 10. SD Timing Input for Timing Mode 1

t3

t1

t6

t2

t7

t5

SDA

SCLK

t3

t4

t8

Figure 11. MPU Port Timing Diagram

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