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CDB5381 Scheda tecnica(PDF) 10 Page - Cirrus Logic |
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CDB5381 Scheda tecnica(HTML) 10 Page - Cirrus Logic |
10 / 24 page 10 DS563F2 CS5381 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (Logic “0” = GND = 0 V; Logic “1” = VL, CL = 20 pF) Parameter Symbol Min Typ Max Unit Output Sample Rate Single-Speed Mode Double-Speed Mode Quad-Speed Mode Fs Fs Fs 2 50 100 - - - 54 108 216 kHz kHz kHz OVFL to LRCK Edge Setup Time tsetup 16/fsclk -- s OVFL to LRCK Edge Hold Time thold 1/fsclk -- s OVFL time-out on overrange condition Fs = 44.1, 88.2, 176.4 kHz Fs = 48, 96, 192 kHz - - 740 680 - - ms ms MCLK Specifications MCLK Period tclkw 36 - 1953 ns MCLK Duty Cycle 40 - 60 % Master Mode SCLK falling to LRCK transition tmslr -20 - 20 ns SCLK falling to SDOUT valid tsdo - - 32 ns SCLK Duty Cycle -50 - % Slave Mode Single-Speed Output Sample Rate Fs 2 - 54 kHz LRCK Duty Cycle 40 50 60 % SCLK Period tsclkw 145 - - ns SCLK Duty Cycle 45 50 55 % SDOUT valid before SCLK rising tstp 10 - - ns SDOUT valid after SCLK rising thld 5- - ns SCLK falling to LRCK transition tslrd -20 - 20 ns Double-Speed Output Sample Rate Fs 50 - 108 kHz LRCK Duty Cycle 40 50 60 % SCLK Period tsclkw 145 - - ns SCLK Duty Cycle 45 50 55 % SDOUT valid before SCLK rising tstp 10 - - ns SDOUT valid after SCLK rising thld 5- - ns SCLK falling to LRCK transition tslrd -20 - 20 ns Quad-Speed Output Sample Rate Fs 100 - 216 kHz LRCK Duty Cycle 40 50 60 % SCLK Period tsclkw 72 - - ns SCLK Duty Cycle 45 50 55 % SDOUT valid before SCLK rising tstp 10 - - ns SDOUT valid after SCLK rising thld 5- - ns SCLK falling to LRCK transition tslrd -8 - 8 ns |
Codice articolo simile - CDB5381 |
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Descrizione simile - CDB5381 |
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