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CAT24FC02JITE13REV-F Scheda tecnica(PDF) 4 Page - Catalyst Semiconductor

Il numero della parte CAT24FC02JITE13REV-F
Spiegazioni elettronici  The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
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Produttore elettronici  CATALYST [Catalyst Semiconductor]
Homepage  http://www.catalyst-semiconductor.com
Logo CATALYST - Catalyst Semiconductor

CAT24FC02JITE13REV-F Scheda tecnica(HTML) 4 Page - Catalyst Semiconductor

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CAT24FC02
4
Doc. No. 1072, Rev. G
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
FUNCTIONAL DESCRIPTION
The CAT24FC02 supports the I2C Bus data transmission
protocol. This Inter-Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter
and any device receiving data to be a receiver. Data
transfer is controlled by the Master device which
generates the serial clock and all START and STOP
conditions for bus access. The CAT24FC02 operates as
a Slave device. Both the Master and Slave devices can
operate as either transmitter or receiver, but the Master
device controls which mode is activated. A maximum of
8 devices may be connected to the bus as determined by
the device address inputs A0, A1, and A2.
PIN DESCRIPTIONS
SCL: Serial Clock
The CAT24FC02 serial clock input pin is used to clock all
data transfers into or out of the device. This is an input
pin.
SDA: Serial Data/Address
The CAT24FC02 bidirectional serial data/address pin is
used to transfer data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed with
other open drain or open collector outputs.
A0, A1, A2: Device Address Inputs
These inputs set device address when cascading multiple
devices. A maximum of eight devices can be cascaded
when using the device.
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. For CAT24FC02 when this pin is tied
to VCC, the entire array of memory is write protected.
When left floating, memory is unprotected.
START BIT
SDA
STOP BIT
SCL
Figure 3. Start/Stop Timing
Figure 2. Write Cycle Timing
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
ACK
8TH BIT
BYTE n
SCL
SDA
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tF
tLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA
tDH
Figure 1. Bus Timing


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