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CAT24FC02GYETE13REV-E Scheda tecnica(PDF) 7 Page - Catalyst Semiconductor |
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CAT24FC02GYETE13REV-E Scheda tecnica(HTML) 7 Page - Catalyst Semiconductor |
7 / 10 page CAT24FC02 7 Doc No. 1072, Rev. G © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Read Operations The READ operation for the CAT24FC02 is initiated in the same manner as the write operation with the one exception that the R/ W bit is set to a one. Three different READ operations are possible: Immediate Address READ, Selective READ and Sequential READ. Immediate Address Read The CAT24FC02 address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N + 1. If N = 255, the counter will ‘wrap around’ to address 0 and continue to clock out data. After the CAT24FC02 receives its slave address information (with the R/ W bit set to one), it issues an acknowledge, then transmits the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Selective Read Selective READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte address of the location it wishes to read. After the CAT24FC02 acknowledge the word address, the Master device resends the START condition and the slave address, this time with the R/ W bit set to one. The CAT24FC02 then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Sequential Read The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT24FC02 sends the initial 8-bit data requested, the Master will respond with an acknowledge which tells the device it requires more data. The CAT24FC02 will continue to output a byte for each acknowledge sent by the Master. The operation will terminate operation when the Master fails to respond with an acknowledge, thus sending the STOP condition. The data being transmitted from the CAT24FC02 is outputted sequentially with data from address N followed by data from address N + 1. The READ operation address counter increments all of the CAT24FC02 address bits so that the entire memory array can be read during one operation. If more than the 256 bytes are read out, the counter will “wrap around” and continue to clock out data bytes. Figure 8. Immediate Address Read Timing SCL SDA 8TH BI 89 T STOP NO ACK DATA OUT SLAVE ADDRESS S A C K DATA N O A C K S T O P P BUS ACTIVITY: MASTER SDA LINE S T A R T |
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