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CD4051B-Q1 Scheda tecnica(PDF) 7 Page - Texas Instruments |
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CD4051B-Q1 Scheda tecnica(HTML) 7 Page - Texas Instruments |
7 / 18 page CD4051BQ1, CD4052BQ1, CD4053BQ1 CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION SCHS354 − AUGUST 2004 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics, VSUPPLY = ±5 V, AV = 1 V, RL = 100 Ω, unless otherwise noted (see Note 2) (continued) PARAMETER TEST CONDITIONS VEE VDD LIMITS AT INDICATED TEMPERATURES UNIT PARAMETER TEST CONDITIONS VEE (V) VDD (V) −40 °C 125 °C 25 °C UNIT (V) (V) −40 °C 125 °C MIN TYP MAX Control (Address or Inhibit), VC VIL = VDD through 1kΩ, V = V through 1k , VSS 5 1.5 1.5 1.5 VIL Input low voltage VIL = VDD through 1k , VIH = VDD through 1kΩ, RL = 1kΩ to VSS, VSS 10 3 3 3 V VIL Input low voltage RL = 1kΩ to VSS, Iis < 2 µA on all OFF channels VSS 15 4 4 4 V VIL = VDD through 1kΩ, V = V through 1k , VSS 5 3.5 3.5 3.5 VIH Input high voltage VIL = VDD through 1k , VIH = VDD through 1kΩ, RL = 1kΩ to VSS, VSS 10 7 7 7 V VIH Input high voltage RL = 1kΩ to VSS, Iis < 2 µA on all OFF channels VSS 15 11 11 11 V IIN Input current VIN = 0 V, 18 V 18 ±0.1 ±1 ±10−5 ±0.1 µA Address-to-signal tr, tf = 20 ns, CL = 50 pF, 0 5 450 720 tpd1 Address-to-signal OUT (channels ON tr, tf = 20 ns, CL = 50 pF, RL = 10 kΩ, VSS = 0 V, 0 10 160 320 ns tpd1 OUT (channels ON or OFF) propagation delay RL = 10 kΩ, VSS = 0 V, See Figure 10, Figure 11, and Figure 14 0 15 120 240 ns or OFF) propagation delay See Figure 10, Figure 11, and Figure 14 −5 5 225 450 Inhibit-to-signal t , t = 20 ns, C = 50 pF, 0 5 400 720 tpd2 Inhibit-to-signal OUT (channel tr, tf = 20 ns, CL = 50 pF, RL = 1 kΩ, VSS = 0 V 0 10 160 320 ns tpd2 OUT (channel turning ON) propagation delay rf L RL = 1 kΩ, VSS = 0 V, See Figure 11 0 15 120 240 ns turning ON) propagation delay See Figure 11 −10 5 200 400 Inhibit-to-signal t , t = 20 ns, C = 50 pF, 0 5 200 450 tpd3 Inhibit-to-signal OUT (channel tr, tf = 20 ns, CL = 50 pF, RL = 10 kΩ, VSS = 0 V 0 10 90 210 ns tpd3 OUT (channel turning OFF) propagation delay rf L RL = 10 kΩ, VSS = 0 V, See Figure 15 0 15 70 160 ns turning OFF) propagation delay See Figure 15 −10 5 130 300 CIN Input capacitance, any address or inhibit input 5 7.5 pF NOTES: 2: Peak-to-peak voltage symmetrical about VDD − VEE 2 3: Determined by minimum feasible leakage measurement for automatic testing |
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