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MVTX2803AG Scheda tecnica(PDF) 1 Page - Zarlink Semiconductor Inc |
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MVTX2803AG Scheda tecnica(HTML) 1 Page - Zarlink Semiconductor Inc |
1 / 127 page 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved. Features • Eight Gigabit Ports with GMII and PCS interface - Gigabit Port can also support 100/10 Mbps MII interface • High Performance Layer 2 Packet Forwarding (23.808M packets per second) and Filtering at Full-Wire Speed • Maximum throughput is 8 Gbps non-blocking • Centralized shared-memory architecture • Consists of two Memory Domains at 133 MHz - Frame Buffer Domain: Two banks of ZBT-SRAM with 2M/4MB total - Switch Database Domain with 256K/512K SRAM • Up to 64K MAC addresses to provide large node aggregation in wiring closet switches Traffic Classification • Classify traffic into 8 transmission priorities per port • Supports Delay bounded, Strict Priority and WFQ • Provides 2 level dropping precedence with WRED mechanism - User controlled thresholds for WRED • Classification based on layer 2, 3 markings - VLAN Priority field in VLAN tagged frame - DS/TOS field in IP packet • The precedence of above two classifications can be programmable October 2003 Ordering Information MVTX2803AG 596 Pin HSBGA -40 °C to +85°C MVTX2803 Unmanaged 8-Port 1000 Mbps Ethernet Switch Data Sheet Figure 1 - MVTX2803AG Block Diagram Frame Data Buffer A ZBT-SRAM (1M/2Mb) Frame Data Buffer B ZBT-SRAM (1M/2Mb) SRAM 256/512K SW Database Schedule GMII /PCS Port 0 GMII /PCS Port 1 GMII /PCS Port 2 GMII /PCS Port 3 GMII /PCS Port 4 GMII /PCS Port 5 GMII /PCS Port 6 GMII /PCS Port 7 NM Database FDB Interface SDB Interface MVTX2803 MAC Table LED Frame Engine Search Engine 32-Bit 64-Bit 64-Bit Management Module Serial / I2C |
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