MTVX2602 datasheet(11/147 Pages) ZARLINK

Il numero della parte	MTVX2602

Spiegazioni elettronici	Managed 24 Port 10/100 Mbps Ethernet Switch

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Produttore elettronici	ZARLINK [Zarlink Semiconductor Inc]

Homepage	http://www.zarlink.com

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11 / 147 page

MVTX2602

Data Sheet

List of Figures

11

Zarlink Semiconductor Inc.

Figure 1 - MVTX2602 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2 - Overview of the MVTX2602 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 3 - Data Transfer Format for I²C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 4 - MVTX2602 SRAM Interface Block Diagram (DMAs for 10/100 Ports Only) . . . . . . . . . . . . . . . . . . . . . 20

Figure 5 - Priority Classification Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 6 - Options for Memory Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 7 - Memory Configuration for 1 Bank, 1 Layer, 1 MB Total . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 8 - Memory Configuration for: 1 Bank, 2 Layers, 2 MB Total . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 9 - Memory Configuration for 1 Bank, 1 Layer, 2 MB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 10 - Buffer Partition Scheme Used to Implement MVTX2602 Buffer Management . . . . . . . . . . . . . . . . . . 37

Figure 11 - GPSI (7WS) Mode Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 12 - SCAN LINK and SCAN COLLISON Status Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 13 - Timing Diagram of LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 14 - Typical Reset & Bootstrap Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Figure 15 - Typical CPU Timing Diagram for a CPU Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Figure 16 - Typical CPU Timing Diagram for a CPU Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 17 - Local Memory Interface – Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Figure 18 - Local Memory Interface – Output Valid Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Figure 19 - AC Characteristics - Reduce Media Independent Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Figure 20 - AC Characteristics – Reduced Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Figure 21 - AC Characteristics – LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Figure 22 - SCANLINK SCANCOL Output Delay Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Figure 23 - SCANLINK, SCANCOL Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Figure 24 - MDIO Input Setup and Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Figure 25 - MDIO Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Figure 26 - I²C Input Setup Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Figure 27 - I²C Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Figure 28 - Serial Interface Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Figure 29 - Serial Interface Output Delay Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

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