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A6150 Datasheet(Scheda tecnica) 6 Page - List of Unclassifed Manufacturers

Numero della parte A6150
Dettagli  High Efficiency Linear Power Supply with Power Surveillance and Software Monitoring
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6
A6150
Pin Description
Pin Name
Function
1EN
Vers. A0:
Open drain active low enable output.
EN must be pulled to V
OUTPUT
even if unused
Vers. A1:
Push-pull active low reset output
2
RES
Open drain active low reset output.
RES must be pulled up to V
OUTPUT
even if unused
3
TCL
Watchdog timer clear input signal
4V
SS
GND terminal
5
INPUT
Voltage regulator input
6
OUTPUT Voltage regulator output
7R
R
EXT input for RC oscillator tuning
8V
IN
Voltage comparator input
Table 5
Functional Description
Voltage Regulator
The A6150 has a 5 V ± 2%, 100 mA, low dropout volt-
age regulator. The low supply current (typ.155 µA) mak-
es the A6150 particularly suited to automotive systems
then remain energized 24 hours a day. The input voltage
range is 2.3 V to 26 V for operation and the input protec-
tion includes both reverse battery (20 V below ground)
and load dump (positive transients up to 60 V). There is
no reverse current flow from the OUTPUT to the INPUT
when the INPUT equals V
SS. This feature is important for
systems which need to implement (with capacitance) a
minimum power supply hold-up time in the event of
power failure. To achieve good load regulation a 22 µF
capacitor (or greater ) is needed on the INPUT (see
Fig. 18). Tantalum or aluminium electrolytics are adequate
for the 22 µF capacitor; film types will work but are relati-
vely expensive. Many aluminium electrolytics have
electrolytes that freeze at about –30 °C, so tantalums are
recommended for operation below –25 °C. The impor-
tant parameters of the 22 µF capacitor are an effective series
resistance of 5 and a resonant frequency
above
500 kHz.
A 10 µF capacitor (or greater) and a 100 nF capacitor are
required on the OUTPUT to prevent oscillations due to
instability. The specification of the 10 µF capacitor is as
per the 22 µF capacitor on the INPUT (see previous
paragraph).
The A6150 will remain stable and in regulation with no
external load and the dropout voltage is typically con-
stant as the input voltage fall to below its minimum level
(see Table 2). These features are especially important in
CMOS RAM keep-alive applications.
Care must be taken not to exceed the maximum junction
temperature (+ 125 °C). The power dissipation within
the A 6150 is given by the formula:
P
TOTAL = (VINPUT – VOUTPUT) * IOUTPUT + (VINPUT) * ISS
The maximum continuous power dissipation at a given
temperature can be calculated using the formula:
P
MAX = ( 125 °C – TA) / Rth(j-a)
where R
th(j-a) is the termal resistance from the junction to
the ambient and is specified in Table 2. Note the R
th(j-a)
given in Table 2 assumes that the package is soldered
to a PCB. The above formula for maximum power dissi-
pation assumes a constant load (ie.100 s). The
transient thermal resistance for a single pulse is much
lower than the continuous value. For example the A6150
in DIP8 package will have an effective thermal resistance
from the junction to the ambient of about 10 °C/W for a
single 100 ms pulse.
VIN Monitoring
The power-on reset and the power-down reset are
generated as a response to the external voltage level
applied on the V
IN input. The VDD voltage at which reset is
asserted or released is determined by the external
voltage divider between V
DD and VSS, as shown on Fig.
18. A part of V
DD is compared to the internal voltage
reference. To determine the values of the divider, the
leakage current at V
IN must be taken into account as well
as the current consumption of the divider itself. Low
resistor values will need more current, but high resistor
values will make the reset threshold less accurate at
high temperature, due to a possible leakage current at
the V
IN input. The sum of the two resistors should stay
below 300 kΩ. The formula is: VRESET = VREF *(1 + R1/R2).
Example: choosing R
1 = 100 k
Ω and R2 = 51 kΩ will
result in a V
DD reset threshold of 4.5 V (typ.).
At power-up the reset output (RES) is held low (see
Fig. 4). After INPUT reaches 3.36 V (and so OUTPUT
reaches at least 3 V) and V
IN becomes greater than VREF,
the RES output is held low for an additional power-on-
reset (POR) delay which is equal to the watchdog time
T
WD (typically 100 ms with an external resistor of 123 k
connected at R pin). The POR delay prevents repeated
toggling of RES even if V
IN and the INPUT voltage drops
out and recovers. The POR delay allows the micropro-
cessor’s crystal oscillator time to start and stabilize and
ensures correct recognition of the reset signal to the
microprocessor.
The RES output goes active low generating the power-
down reset whenever V
IN falls below VREF. The sensiti-
vity or reaction time of the internal comparator to the vol-
tage level on V
IN is typically 5 µs.
Timer Programming
The on-chip oscillator with an external resistor R
EXT con-
nected between the R pin and V
SS (see Fig. 18) allows
the user to adjust the power-on reset (POR) delay,
watchdog time T
WD and with this also the closed and
open time windows as well as the watchdog reset pulse
width (T
WD/40).
With R
EXT = 123 ktypical values are:
-Power-on reset delay: T
POR is 100 ms
-Watchdog time:
T
WD is 100 ms




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