AD8065 datasheet(6/32 Pages) AD

Il numero della parte	AD8065

Spiegazioni elettronici	Dual 8-,10-,12-Bit High Bandwidth Multiplying DACs with Serial Interface

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Produttore elettronici	AD [Analog Devices]

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AD5429/AD5439/AD5449

Rev. 0 | Page 6 of 32

t1

t2

t3

t7

t8

t4

t5

t6

t9

t10

t11

DB15

DB0

SCLK

DIN

LDAC1

LDAC2

SYNC

NOTES

1ASYNCHRONOUS LDAC UPDATE MODE

2SYNCHRONOUS LDAC UPDATE MODE

ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS

DETERMINED BY CONTROL BITS. TIMING AS ABOVE, WITH SCLK INVERTED.

Figure 2. Standalone Mode Timing Diagram

t8

t7

t12

t1

t3

t2

t4

t5

t6

DB15

(N)

DB15

(N+1)

DB0

(N)

DB0

(N+1)

DB15

(N)

DB0

(N)

SCLK

SYNC

SDIN

SDO

ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS

DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING

EDGE OF SCLK. TIMING AS ABOVE, WITH SCLK INVERTED.

Figure 3. Daisy-Chain and Readback Modes Timing Diagram

200

µAI

OL

200

µAI

OH

TO OUTPUT

CL

50pF

VOH (MIN) + VOL (MAX)

2

Figure 4. Load Circuit for SDO Timing Specifications

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