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TDA6501 Scheda tecnica(PDF) 9 Page - NXP Semiconductors |
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TDA6501 Scheda tecnica(HTML) 9 Page - NXP Semiconductors |
9 / 37 page 9397 750 15057 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 02 — 14 June 2005 9 of 37 Philips Semiconductors TDA6500; TDA6501 5 V mixer/oscillator and synthesizer for PAL and NTSC standards 7.2.2 Read mode Data can be read from the device by setting the R/W bit to logic 1. The data read format is shown in Table 11. After the slave address has been recognized, the device generates an acknowledge pulse and the first data byte (status byte) is transferred on the SDA line with the MSB first. Data is valid on the SDA line during a HIGH-level of the SCL clock signal. A second data byte can be read from the device if the microcontroller generates an acknowledge on the SDA line (master acknowledge). End of transmission will occur if no master acknowledge occurs. The device will then release the data line to allow the microcontroller to generate a STOP condition. The POR flag is set to logic 1 at power-on. The flag is reset when an end-of-data is detected by the device (end of a read sequence). Control of the loop is made possible with the in-lock flag (FL) which indicates when the loop is locked (FL = 1). The internal AGC status is available from the AGC bit. AGC = 1 indicates when the selected take-over point is reached. A built-in ADC is available on the P6/ADC pin. The ADC can be used to apply AFC information to the microcontroller from the IF section of the tuner. The relationship between the voltage applied to the ADC input and the A2, A1 and A0 bits is given in Table 13. [1] MSB is transmitted first. Table 11: Read data format Name Byte Bit Ack MSB [1] LSB Address byte ADB 1 1000MA1 MA0 R/W=1 A Status byte SB POR FL 1 1 AGC A2 A1 A0 - Table 12: Description of bits shown in Table 11 Symbol Description A acknowledge MA1 and MA0 programmable address bits; see Table 7 R/W logic 1 for read mode POR power-on reset flag POR = 0, normal operation POR = 1, power-on state FL in-lock flag FL = 0, not locked FL = 1, the PLL is locked AGC internal AGC flag AGC = 0, internal AGC not active AGC = 1, internal AGC is active; level below 3 V A2, A1 and A0 digital output of the 5-level ADC; see Table 13 |
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