TC3299A

Preliminary Data Sheet

PJ1,0 : If MA12 isn't pulled low during power on reset, despite of the value of PJ1,0, TC3299A response

to I/O access at the I/O base address 300h, 320h, 340h, 360h. otherwise, I/O base Map as below:

PJ1

PJ0

I/O base Map

0

0

300h

0

1

320h

1

0

340h

1

1

360h

PJ1,0

: Reserved

Configuration Registers 1 ® (CCR1)

7

6

5

4

3

2

1

0

XX

XX

XX

XX

XX

XX

IREQ

XX

IREQ

: Controller interrupt status

XX

: Reserved

2.1

Power On Configuration

The EPCC Controller configures itself after a RST signal is applied. When a Power-On-Reset occurs the

EPCC Controller latches the values on the configuration pins and uses these to configure the internal

registers and options. Internally these pins contain pull-up resistance. If these configuration pins are

unconnected the default logic will be applied. The configuration registers are loaded from the memory data

bus when RST goes inactive.

A Power-On-Reset also causes the EPCC Controller to load the internal PROM store from the EEPROM,

which can take up to 3 ms. This occurs after Config-Regs (Configuration registers?) have completed. If

EECONFIG is high (MA9 pull down) the configuration data loaded on the falling edge of RST will be

overwritten by the data read from the serial EEPROM. Regardless of the level on EECONFIG the PROM

store will always be loaded with data from the serial EEPROM during the time specified as EELOAD.

Figure 1 shows how the RESET circuitry operates.

VCC

RESET

Regload

EEload

The EPCC Controller users an 93C56/66, The programmed contents of the EEPROM is shown as following.

D15

D0

......

CIS byte n

CIS byte n-1

......

16H

........

........

14H

........

........

12H

CIS byte 3

CIS byte 2

Confidential.

9/26

August 27, 20003

Copyright © 2003, IC Plus Corp.

TC3299A-DS-R30