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CDCV857DGG Scheda tecnica(PDF) 1 Page - Texas Instruments

Il numero della parte CDCV857DGG
Spiegazioni elettronici  2.5-V PHASE LOCK LOOP CLOCK DRIVER
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CDCV857DGG Scheda tecnica(HTML) 1 Page - Texas Instruments

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CDCV857
2.5-V PHASE LOCK LOOP CLOCK DRIVER
SCAS645A – AUGUST 2000 – REVISED OCTOBER 2000
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Phase-Lock Loop Clock Driver for Double
Data-Rate Synchronous DRAM
Applications
D Spread Spectrum Clock Compatible
D Operating Frequency: 60 to 200 MHz
D Low Jitter (cyc–cyc): ±75 ps
D Distributes One Differential Clock Input to
Ten Differential Outputs
D Three-State Outputs When the Input
Differential Clocks Are <20 MHz
D Operates From Dual 2.5-V Supplies
D 48-Pin TSSOP Package
D Consumes < 200-µA Quiescent Current
D External Feedback PIN (FBIN, FBIN) Are
Used to Synchronize the Outputs to the
Input Clocks
description
The CDCV857 is a high-performance, low-skew,
low-jitter zero delay buffer that distributes a
differential clock input pair (CLK, CLK) to ten
differential pairs of clock outputs (Y[0:9], Y[0:9])
and one differential pair of feedback clock output
(FBOUT,
FBOUT).
The
clock
outputs
are
controlled by the clock inputs (CLK, CLK), the
feedback clocks (FBIN, FBIN), and the analog
power input (AVDD). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When
PWRDWN is low, all outputs are disabled to high impedance state (3-state), and the PLL is shut down (low power
mode). The device also enters this low power mode when the input frequency falls below a suggested detection
frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit will detect the low
frequency condition and after applying a >20 MHz input signal this detection circuit turns on the PLL again and
enables the outputs.
When AVDD is strapped low, the PLL is turned off and bypassed for test purposes. The CDCV857 is also able
to track spread spectrum clocking for reduced EMI.
Since the CDCV857 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.
This stabilization time is required following power up. The CDCV857 is characterized for operation from 0
°C
to 85
°C.
Copyright
© 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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GND
Y0
Y0
VDDQ
Y1
Y1
GND
GND
Y2
Y2
VDDQ
VDDQ
CLK
CLK
VDDQ
AVDD
AGND
GND
Y3
Y3
VDDQ
Y4
Y4
GND
GND
Y5
Y5
VDDQ
Y6
Y6
GND
GND
Y7
Y7
VDDQ
PWRDWN
FBIN
FBIN
VDDQ
FBOUT
FBOUT
GND
Y8
Y8
VDDQ
Y9
Y9
GND
DGG PACKAGE
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