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NV25080LV Scheda tecnica(PDF) 3 Page - ON Semiconductor |
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NV25080LV Scheda tecnica(HTML) 3 Page - ON Semiconductor |
3 / 20 page NV25080LV, NV25160LV, NV25320LV, NV25640LV www.onsemi.com 3 Table 4. PIN CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = +5.0 V) (Note 2) Symbol Test Conditions Min Typ Max Unit COUT Output Capacitance (SO) VOUT = 0 V 8 pF CIN Input Capacitance (CS, SCK, SI, WP, HOLD) VIN = 0 V 8 pF Table 5. AC CHARACTERISTICS (Note 4) Symbol Parameter VCC 3 2.5 V VCC = 2.5 V to 4.5 V VCC = 4.5 V to 5.5 V Unit Min Max Min Max Min Max fSCK Clock Frequency DC 5 DC 10 DC 20 MHz tSU Data Setup Time 20 10 5 ns tH Data Hold Time 20 10 5 ns tWH SCK High Time 75 40 20 ns tWL SCK Low Time 75 40 20 ns tLZ HOLD to Output Low Z 50 25 25 ns tRI (Note 5) Input Rise Time 2 2 2 ms tFI (Note 5) Input Fall Time 2 2 2 ms tHD HOLD Setup Time 0 0 0 ns tCD HOLD Hold Time 10 10 5 ns tV Output Valid from Clock Low 75 40 20 ns tHO Output Hold Time 0 0 0 ns tDIS Output Disable Time 50 20 20 ns tHZ HOLD to Output High Z 100 25 25 ns tCS CS High Time 80 40 20 ns tCSS CS Setup Time 60 30 15 ns tCSH CS Hold Time 60 30 15 ns tCNS CS Inactive Setup Time 60 30 15 tCNH CS Inactive Hold Time 60 30 15 tWC (Note 6) Write Cycle Time 4 4 4 ms 4. AC Test Conditions: Input Pulse Voltages: 0.3 VCC to 0.7 VCC at VCC > 2.5 V, 0.2 VCC to 0.8 VCC at VCC < 2.5 V Input rise and fall times: ≤ 10 ns Input and output reference voltages: 0.5 VCC Output load: current source IOL max/IOH max; CL = 30 pF 5. This parameter is tested initially and after a design or process change that affects the parameter. 6. tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle. Table 6. POWER−UP TIMING (Notes 5, 7) Symbol Parameter Max Unit tPUR Power−up to Read Operation 0.35 ms tPUW Power−up to Write Operation 0.35 ms 7. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. |
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